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STA016T 数据表(PDF) 24 Page - STMicroelectronics

部件名 STA016T
功能描述  MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM
PDF  45 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA016T 数据表(HTML) 24 Page - STMicroelectronics

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I_AUDIO_CONFIG_8 :
Address : 0x62 (98)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, those registers are used to
configure the MASK to be appllied to CD_LRCK &
BS_LRCK phase 1 & 2.
– if MAi set to 0, then bit i of both phases is not
received.
– if MAi set to 1, then bit i of both phases is re-
ceived.
I_AUDIO_CONFIG_9 :
Address : 0x63 (99)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate the size of the data to be received by CD & BS
input interfaces in audio mode. Max is 32.
I_AUDIO_CONFIG_10 :
Address : 0x64 (100)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_11 register description.
I
I_AUDIO_CONFIG_11 :
Address : 0x65 (101)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, those registers are used to
create BCK if configurated in output (so if CF2=1 &
CF5=1): then value of DV[15:0] is the divider factor to
be applied to the selected clock (CF11 select either
SYSCLK or PCMCLK) to create BCK.
Note : value 0 & 1 correspond to a bypass of the di-
viders.
3.7 BSB_CONFIGURATION registers
description
POL_REQ :
Address : 0x59 (89)
Type : WO - DEC
Software Reset : 0
Description :
This register manage the polarity of the data REQ
signal DREQ of the BS input interface.
If set to 0, data are requested when REQ = 0.
If set to 1, data are requested when REQ = 1.
INPUT_CONF :
Address : 0x5A (90)
Type : RW - DEC
Software Reset : 0
Description :
b7
b6
b5
b4
b3
b2
b1
b0
MA31 MA30 MA29 MA28 MA27 MA26 MA25 MA24
b7
b6
b5
b4
b3
b2
b1
b0
DL7
DL6
DL5
DL4
DL3
DL2
DL1
DL0
b7
b6
b5
b4
b3
b2
b1
b0
DV7
DV6
DV5
DV4
DV3
DV2
DV1
DV0
b7
b6
b5
b4
b3
b2
b1
b0
DV15 DV14 DV13 DV12 DV11 DV10
DV9
DV8
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0



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