LP8556 datasheet(30/63 Pages) TI1

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ADR6

Bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

C SLAVE address (chip address)

LP8556

SNVS871I – JULY 2012 – REVISED MARCH 2016

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Programming (continued)

8.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP8556 operates as a slave device with 7-bit address

combined with data direction bit. Slave address is 2Ch as 7-bit or 58h for write and 59h for read in 8-bit format.

Before any data is transmitted, the master transmits the slave I.D. The slave device should send an acknowledge

signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends

on the bit sent after the slave address — the 8th bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

Figure 16. I2C Chip Address (0x2C)

8.5.1.6 Control Register Write Cycle

•

Master device generates start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master sends data byte to be written to the addressed register.

•

Slave sends acknowledge signal.

•

If master sends further data bytes the control register address is incremented by one after acknowledge

signal.

•

Write cycle ends when the master creates stop condition.

8.5.1.7 Control Register Read Cycle

•

Master device generates a start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master device generates repeated start condition.

•

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

•

Slave sends acknowledge signal if the slave address is correct.

•

Slave sends data byte from addressed register.

•

If the master device sends acknowledge signal, the control register address is incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

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