SWCS049G datasheet(76/119 Pages) TI1

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TPS659110, TPS659112, TPS659113

TPS659114, TPS659118, TPS6591133

SWCS049Q – JUNE 2010 – REVISED MARCH 2016

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Detailed Description

Reserved

SEL

Bits

Field Name

Description

Type

Reset

Reserved

Reserved bit

R returns

6:0

SEL

Output voltage selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):

SEL[6:0] = 1001011 to 1111111: 1.5 V

...

SEL[6:0] = 0111111: 1.35 V

...

SEL[6:0] = 0110011: 1.2 V

...

SEL[6:0] = 0000001 to 0000011: 0.6 V

SEL[6:0] = 0000000: Off (0.0 V)

Note: from SEL[6:0] = 3 to 75 (dec)

Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G

(Default value: See boot configuration)

Note: Vout maximum value is 3.3 V

0x00

Table 6-39. VDD2_REG

Address Offset

0x24

Physical Address

Instance

(RESET DOMAIN: TURNOFF OFF

RESET)

Description

VDD2 control register

Type

VGAIN_SEL

ILMAX

TSTEP

Bits

Field Name

Description

Type

Reset

7:6

VGAIN_SEL

Select output voltage multiplication factor (×1, ×3 included in EEPROM

bits): G

when 00: ×1

when 01: ×1

when 10: ×2

when 11: ×3

0x0

ILMAX

Select maximum load current:

when 0: 1.0 A

when 1: > 1.5 A

4:2

TSTEP

Time step: when changing the output voltage, the new value is reached

through successive 12.5-mV voltage steps (if not bypassed). The

equivalent programmable slew rate of the output voltage is then:

TSTEP[2:0] = 000: step duration is 0, step function is bypassed

TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 MHz)

TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 MHz × 3/4)

TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 MHz × 3/5) (default)

TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 MHz/2)

TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 MHz/3)

TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 MHz/4)

TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 MHz/5)

0x1

1:0

Supply state (EEPROM bits):

ST[1:0] = 00: Off

ST[1:0] = 01: On, high-power mode

ST[1:0] = 10: Off

ST[1:0] = 11: On, low-power mode

0x0

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