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SWCS049G 数据表(PDF) 87 Page - Texas Instruments |
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SWCS049G 数据表(HTML) 87 Page - Texas Instruments |
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87 / 119 page  87 TPS659110, TPS659112, TPS659113 TPS659114, TPS659118, TPS6591133 www.ti.com SWCS049Q – JUNE 2010 – REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133 Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated Table 6-59. SLEEP_KEEP_RES_ON_REG Address Offset 0x42 Physical Address Instance Description Configuration Register keeping, during the SLEEP state of the device (but then supply state can be overwritten programming ST[1:0]): - the full load capability of LDO regulator (ACTIVE mode), - The PWM mode of DCDC converter - 32-kHz clock output - Register access though I2C interface (keeping the internal high speed clock on) - Die Thermal monitoring on Control bit value has no effect if the resource is off. Type RW 7 6 5 4 3 2 1 0 THERM_ KEEPON CLKOUT32K_ KEEPON VRTC_ KEEPON I2CHS_ KEEPON Reserved VDD2_ KEEPON VDD1_ KEEPON VIO_ KEEPON Bits Field Name Description Type Reset 7 THERM_KEEPON When 1, thermal monitoring is maintained during device SLEEP state. When 0, thermal monitoring is turned off during device SLEEP state. RW 0 6 CLKOUT32K_KEEPO N When 1, CLK32KOUT output is maintained during device SLEEP state. When 0, CLK32KOUT output is set low during device SLEEP state. RW 0 5 VRTC_KEEPON When 1, LDO regulator full load capability (ACTIVE mode) is maintained during device SLEEP state. When 0, the LDO regulator is set or stays in low-power mode during device SLEEP state. RW 0 4 I2CHS_KEEPON When 1, high speed internal clock is maintained during device SLEEP state. When 0, high speed internal clock is turned off during device SLEEP state. RW 0 3 Reserved RO 0 2 VDD2_KEEPON When 1, VDD2 SMPS PWM mode is maintained during device SLEEP state. No effect if VDD2 working mode is PFM. When 0, VDD2 SMPS PFM mode is set during device SLEEP state. RW 0 1 VDD1_KEEPON When 1, VDD1 SMPS PWM mode is maintained during device SLEEP state. No effect if VDD1 working mode is PFM. When 0, VDD1 SMPS PFM mode is set during device SLEEP state. RW 0 0 VIO_KEEPON When 1, VIO SMPS PWM mode is maintained during device SLEEP state. No effect if VIO working mode is PFM. When 0, VIO SMPS PFM mode is set during device SLEEP state. RW 0 Table 6-60. SLEEP_SET_LDO_OFF_REG Address Offset 0x43 Physical Address Instance (RESET DOMAIN: GENERAL RESET) Description Configuration Register turning-off LDO regulator during the SLEEP state of the device. Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON register should be 0 to make this *_SET_OFF control bit effective Type RW 7 6 5 4 3 2 1 0 LDO3_SETOFF LDO4_SETOFF LDO7_SETOFF LDO8_SETOFF LDO5_SETOFF LDO2_SETOFF LDO1_SETOFF LDO6_SETOFF Bits Field Name Description Type Reset 7 LDO3_SETOFF When 1, LDO regulator is turned off during device SLEEP state. When 0, No effect RW 0 6 LDO4_SETOFF When 1, LDO regulator is turned off during device SLEEP state. When 0, No effect RW 0 |
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