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SWCS049G 数据表(PDF) 95 Page - Texas Instruments |
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SWCS049G 数据表(HTML) 95 Page - Texas Instruments |
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95 / 119 page  95 TPS659110, TPS659112, TPS659113 TPS659114, TPS659118, TPS6591133 www.ti.com SWCS049Q – JUNE 2010 – REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133 Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated Bits Field Name Description Type Reset 7 PWRDN_IT_MSK PWRDN interrupt mask RW 1 6 VMBCH2_L_IT_MSK Comparator2 input below threshold detection interrupt mask RW 1 5 VMBCH2_H_IT_MSK Comparator2 input above threshold detection interrupt mask RW 1 4 WTCHDG_IT_MSK Watchdog interrupt mask. RW 1 3 GPIO5_F_IT_MSK GPIO5 falling-edge detection interrupt mask. RW 1 2 GPIO5_R_IT_MSK GPIO5 rising-edge detection interrupt mask. RW 1 1 GPIO4_F_IT_MSK GPIO4 falling-edge detection interrupt mask. RW 1 0 GPIO4_R_IT_MSK GPIO4 rising-edge detection interrupt mask. RW 1 Table 6-72. GPIO0_REG Address Offset 0x60 Physical Address Instance (RESET DOMAIN: GENERAL RESET) Description GPIO0 configuration register Type RW 7 6 5 4 3 2 1 0 GPIO_SLEEP Reserved GPIO_ODEN GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET (1) The GPIO_SLEEP bit is a bit available only for GPIO_0/2/6/7.This bit will be take into account and be effective only if the GPIO_0/2/6/7 is associated to a TIME_SLOT. It means that this bit is useful only if the GPIO is part of the POWER UP SEQUENCE. Note that in this case the associated GPIO will be set as GPO. GPIO_SLEEP bit is a bit related to the PMU sleep mode only, No action in ACTIVE mode. It is used to define SLEEP mode state for GPIO 0/2/6/7. Bits Field Name Description Type Reset 7 GPIO_SLEEP(1) 1: as GPO, force low 0: No impact, keep as in active mode RW 0 6 Reserved Reserved bit RO R returns 0s 0 5 GPIO_ODEN Selection of output mode, EEPROM bit 0: Push-pull output 1: Open-drain output (Default value: See boot configuration) GPIO assigned to power-up sequence, this bit will be set to 1 by a TURNOFF reset RW 0 4 GPIO_DEB GPIO input debouncing time configuration: When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate When 1, the debouncing is 150 ms using a 50 ms clock rate RW 0 3 GPIO_PDEN GPIO pad pulldown control: 1: Pulldown is enabled 0: Pulldown is disabled RW 0 2 GPIO_CFG Configuration of the GPIO pad direction: When 0, the pad is configured as an input When 1, the pad is configured as an output (Default value: See boot configuration) RW 0 1 GPIO_STS Status of the GPIO pad RO 1 0 GPIO_SET Value set on the GPIO output when configured in output mode GPIO assigned to power-up sequence, this bit will be in TURNOFF reset RW 0 Table 6-73. GPIO1_REG Address Offset 0x61 Physical Address Instance (RESET DOMAIN: GENERAL RESET) Description GPIO1 configuration register |
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