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PI6CFGL201B

RevB

03/16/16

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PI6CFGL201B

2-Output Low Power PCIE Gen 1-2-3 Clock Generator

Symbol

Parameters

Condition

Min.

Type

Max. Units

Electrical Characteristics–Input/Supply/Common Parameters

(Based on T

o

C; VDD = 3.3V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions)

t

F

Control inputs

5

ns

t

R

Control inputs

5

ns

V

ILSMB

0.8

V

V

IHSMB

2.1

3.6

V

V

OLSMB

@ I

PULLUP

0.4

V

I

PULLUP

@ V

OL

4

mA

V

DDSMB

3.3V bus voltage

2.7

3.6

V

t

RSMB

(Max VIL - 0.15) to (Min VIH + 0.15)

1000

ns

t

FSMB

(Min VIH + 0.15) to (Max VIL - 0.15)

300

ns

f

MAXSMB

SMBus Operating

Maximum SMBus operating frequency

400

kHz

Electrical Characteristics–CLK 0.7V Low Power HCSL Outputs

(T

o

C; VDD = 3.3V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions)

Symbol

Parameters

Condition

Min. Type Max. Units

trf

Scope averaging on 1.5V/ns setting

0.9

1.4

1.9

V/ns

Scope averaging on 3.0V/ns setting

1.8

2.9

4

V/ns

Δtrf

Slew rate matching, Scope averaging on

20

%

V

OH

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope averaging

on)

660

850

mV

V

OL

-150

150

mV

Vmax

Measurement on single ended signal using

absolute value. (Scope averaging off)

1150

mV

Vmin

-300

mV

Vswing

Scope averaging off

300

mV

Vcross_abs Crossing Voltage (abs)

1,

5, 7

Scope averaging off

250

550

mV

Δ-Vcross

Scope averaging off

140

mV

Note:

1. Guaranteed by design and characterization, not 100% tested in production.

2. Measured from differential waveform

3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.

4. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point

where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calcula-

tions.

5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and

Clock# falling).

6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is

to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.

7. At default SMBus settings.

Note:

1. Guaranteed by design and characterization, not 100% tested in production.

2. Control input must be monotonic from 20% to 80% of input swing. Input Frequency Capacitance

3. Time from deassertion until outputs are >200 mV

4. The differential input clock must be running for the SMBus to be active

15-0134