2

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PI6CFGL201B

RevB

03/16/16

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PI6CFGL201B

2-Output Low Power PCIE Gen 1-2-3 Clock Generator

SMBus Address Selection Table

SADR

Address

+ Read/Write Bit

State of SADR on first application of CKPWRGD_PD#

0

1101000

1/0

1

1101010

1/0

Power Management Table

CKPWRGD_PD#

SMBus OE bit

CLKx

REF1.8

True O/P

Comp. O/P

0

x

Low

Low

1

1

Running

Running

Running

1

0

Low

Low

Low

Note:

1. REF1.8 is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF1.8 is Low.

Output

Input

Typ. 6us

First rise edge

CKPWRGD_PD#

SADR/REF1.8

CKPWRGD_PD#

OE (Pin)

OE (SMBus bit)

CLKx

True O/P

Comp. O/P

0

X

x

Low

Low

1

0

0

Low

Low

1

0

1

Running

Running

1

1

0

Low

Low

1

1

1

Low

Low

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