7

www.pericom.com

PI6CFGL201B

RevB

03/16/16

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PI6CFGL201B

2-Output Low Power PCIE Gen 1-2-3 Clock Generator

Electrical Characteristics–Phase Jitter Parameters

(T

o

C; VDD = 3.3V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions)

Symbol

Parameters

Condition

Min.

Type

INDUSTRY

LIMIT

Units

t

jphPCIeG1

1, 2, 3, 5

Phase Jitter, PCI

Express

PCIe Gen 1

30

86

ps

(p-p)

t

jphPCIeG2

1, 2, 5

PCIe Gen 2 Low Band

10kHz < f < 1.5MHz

0.5

3

ps

(rms)

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

2.2

3.1

ps

(rms)

t

jphPCIeG3

1, 2, 4, 5

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.46

1

ps

(rms)

Notes:

1. Guaranteed by design and characterization, not 100% tested in production.

2. See http://www.pcisig.com for complete specs.

3. Sample size of at least 100k cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

4. Calculated from Intel-supplied Clock Jitter Tool.

5. Applies to all different outputs.

Electrical Characteristics–REF1.8

(T

o

C; VDD = 3.3V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions)

Symbol

Parameters

Condition

Min. Type

Max. Units

ppm

see Tperiod min-max values

0

ppm

T

period

25 MHz output nominal

40

ns

t

rf1

V

0.5

2.5

V/ns

t

DC

V

45

55

%

t

DCD

V

0

3

%

t

jc-c

V

250

ps

t

jdBc1k

1kHz offset

-141

-120

dBc

t

jdBc10k

10kHz offset to Nyquist

-150

-130

dBc

t

jphREF

12kHz to 5MHz

0.46

1

ps

(rms)

Notes:

1. Guaranteed by design and characterization, not 100% tested in production.

2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF1.8 is trimmed to 25.00 MHz.

3. Typical value occurs when REF1.8 slew rate is set to default value.

4. When driven by a crystal.

5. When driven by an external oscillator via the XTAL_IN pin. XTALK_OUT should be floating in this case.

15-0134