IS25LP256

Integrated Silicon Solution, Inc.- www.issi.com

4

Rev.00A

1/16/2014

PIN CONFIGURATION

Notes:

1. According to the P7 bit setting in Read Register, either HOLD# (P7=0) or RESET# (P7=1) pin can be selected.

2.

For the dedicated parts that don’t have the additional RESET# pin on pin3, either HOLD# or RESET# pin can be

selected on pin1 by the P7 bit setting in Read Register when QE=0. For the dedicated parts with additional

RESET# pin on pin3, only HOLD# pin is selected for pin1 regardless of the P7 bit of Read Register when QE=0.

3. The dedicated parts have additional RESET# pin (pin3) on 16-pin SOIC 300mil package. For the parts, Function

Register Bit0 (RESET# Enable/Disable) will be set to “0”. The RESET# pin is independent of the P7 bit of Read

Register and QE bit of Status Register. The RESET# pin has an internal pull-up resistor and may be left floating if

not used. Call Factory for the RESET# pin option.

12

10

11

9

13

15

14

5

7

6

8

4

2

3

16

1

Vcc

HOLD# (IO3)

HOLD# or RESET# (IO3)

SCK

CE#

WP# (IO2)

GND

NC

NC

NC

NC

NC

SI (IO0)

SO (IO1)

NC

NC

RESET#/NC

16-pin SOIC 300mil

(1)

(1)

(3)

(2)

ADVANCED INFORMATION