|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

2-bit bidirectional low voltage translator

2016-01-0001

PT0579

01/27/16

1

PI4GTL2002

Features

 2-bit bidirectional translator

 Less than 1.5 ns maximum propagation delay to

accommodate Standard mode and Fast mode I2C-

bus devices and multiple masters

 Allows voltage level translation between 0.8V, 1.2

V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V buses, which

allows direct interface with GTL, GTL+,

LVTTL/TTL and 5 V CMOS levels

 Provides bidirectional voltage translation with no

direction pin

 Low 3.5 ohm

-state connection between input

and output ports provides less signal distortion

 Supports hot insertion

 5 V tolerant inputs

 Flow through pin out for ease of printed-circuit

board trace routing

 ESD protection exceeds 4KV HBM per JESD22-

A114

Description

The Gunning Transceiver Logic - Transceiver

Voltage Clamps (GTL-TVC) provide high-speed voltage

translation with low ON-state resistance and minimal

propagation delay. The GTL2002 provides 2 NMOS

pass transistors (Sn and Dn) with a common gate (GREF)

and a reference transistor (SREF and DREF). The device

allows bidirectional voltage translations between 0.8 V

and 5.0 V without use of a direction pin.

When the Sn or Dn port is LOW the clamp is in the

ON-state and a low resistance connection exists between

the Sn and Dn ports. Assuming the higher voltage is on

the Dn port, when the Dn port is HIGH, the voltage on

the Sn port is limited to the voltage set by the reference

transistor (SREF). When the Sn port is HIGH, the Dn

port is pulled to VCC by the pull-up resistors. This

functionality allows a seamless translation between

higher and lower voltages selected by the user, without

the need for directional control.

All

transistors

have

the

same

electrical

characteristics and there is minimal deviation from one

output to another in voltage or propagation delay. This is

a benefit over discrete transistor voltage translation

solutions, since the fabrication of the transistors is

symmetrical. Because all transistors in the device are

identical, SREF and DREF can be located on any of the

other two matched Sn/Dn transistors, allowing for easier

board

layout.

The

translator's

transistors

provide

excellent ESD protection to lower voltage devices and at

the same time protect less ESD-resistant devices.

Pin Configuration

MSOP-8L/SOIC-8L(Top View)

UQFN1.6*1.6-8L(Top View)