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ADAV4601BSTZ 数据表(PDF) 53 Page - Analog Devices

部件名 ADAV4601BSTZ
功能描述  Audio Processor for Advanced TV
PDF  60 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAV4601BSTZ 数据表(HTML) 53 Page - Analog Devices

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ADAV4601
Rev. B | Page 53 of 60
Bit No.
Bit Name
Description
Default
Bits[3:1]
Select internally generated
clock
Selects the frequency of the internally generated clock to be output on the MCLK_OUT pin.
000
000b = crystal clock from internal PLL
001b = audio processor clock (122.88 MHz/2560 × FS)
010b = engine clock (49.152 MHz/1024 × FS)
011b = SRC clock/2 (24.576 MHz/512 × FS)
1xxb = modulator clock (6.144 MHz/128 × FS)
Bit[0]
PLL enable
Enables the PLL.
0
0b = PLL bypassed
1b = PLL enabled
Address 0x000B Headphone Control Register (Default: 0x0000)
Table 52.
Bit No.
Bit Name
Description
Default
Bits[15:8]
Reserved
Always write as 0 if writing to this register.
00000000
Bit[7]
HP1 mute
When set to 1, mutes the headphone output immediately without ramping.
0
0b = unmuted
1b = mute
Bit[6]
HP1 short-circuit protect
Enables the short-circuit protection for the headphone amplifier.
0
0b = disabled
1b = enabled
Bit[5]
HP1 tristate
Disables tristating of the headphone amplifier.
0
0b = enabled
1b = disabled
Bits[4:0]
Headphone 1 gain/attenuation
Used to apply analog attenuation to the headphone amplifier.
00000
00000b = 0 dB
00001b = −1.5 dB
00010b = −3 dB
11101b = −43.5 dB
11110b = −45 dB
11111b = +1.5 dB
Address 0x000C Serial Port Control 2 Register (Default: 0x8004)
It should be noted that SDIN3, LRCLK0, BCLK0, LRCLK1, BCLK1, LRCLK2, and BCLK2 can also be used as SPDIF_IN0, SPDIF_IN1,
SPDIF_IN2, SPDIF_IN3, SPDIF_IN4, SPDIF_IN5, and SPDIF_IN6.
Table 53.
Bit No.
Bit Name
Description
Default
Bits[15:14]
SCR2 clock select
Used to select the serial clocks used for the input to SRC2.
10
00b = uses LRCLK0 and BCLK0
01b = uses LRCLK1 and BCLK1
10b = uses LRCLK2 and BCLK2
11b = reserved
Bits[13:12]
SRC1 clock select
Used to select the serial clocks used for the input to SRC1.
00
00b = uses LRCLK0 and BCLK0
01b = uses LRCLK1 and BCLK1
10b = uses LRCLK2 and BCLK2
11b = reserved
Bit[11]
Reserved
Always write as 0 if writing to this register.
0



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