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ADAV4601BSTZ 数据表(PDF) 20 Page - Analog Devices |
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ADAV4601BSTZ 数据表(HTML) 20 Page - Analog Devices |
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20 / 60 page ![]() ADAV4601 Rev. B | Page 20 of 60 I2S DIGITAL AUDIO INPUTS The ADAV4601 has four I2S digital audio inputs that are, by default, synchronous to the master clock. Also available are two SRCs capable of supporting any nonsynchronous input with a sample rate between 5 kHz and 50 kHz. Any of the serial digital inputs can be redirected through the SRC. Figure 26 shows a block diagram of the input serial port. SRC2B SRC2C LRCLK0 BCLK0 LRCLK1 BCLK1 LRCLK2 BCLK2 SDIN0 SDIN1 SDIN2 SDIN3 LRCLK0 BCLK0 SDIN0 SDIN1 SDIN2 SDIN3 LRCLK1 BCLK1 LRCLK2 BCLK2 SRC1 LRCLK0 BCLK0 SDIN0 SDIN1 SDIN2 SDIN3 LRCLK1 BCLK1 LRCLK2 BCLK2 SRC2 SRC2A SRC2B SRC2C AUDIO PROCESSOR Figure 26. Digital Input Section Synchronous Inputs and Outputs The synchronous digital inputs and outputs can use any of the BCLK or LRCLK inputs as a clock and framing signal. By default, BCLK1 and LRCLK1 are the serial clocks used for the synchronous inputs. The synchronous port for the ADAV4601 is in slave mode by default, which means the user must supply the appropriate serial clocks, BCLK and LRCLK. The synchronous port can also be set to master mode, which means that the appropriate serial clocks, BCLK and LRCLK, can be generated internally from the MCLK; therefore, the user does not need to provide them. The serial data inputs are capable of accepting all of the popular audio transmission standards (see the Serial Data Interface section for more details). Asynchronous Inputs The ADAV4601 has two SRCs, SRC1 and SRC2, that can be used for converting digital data, which is not synchronous to the master clock. Each SRC can accept input sample rates in the range of 5 kHz to 50 kHz. Data that has been converted by the SRC is input to the part and is then synchronous to the internal audio processor. The SRC1 is a 2-channel (single-stereo) sample rate converter that is capable of using any of the three serial clocks available. The SRC1 can accept data from any of the serial data inputs (SDIN0, SDIN1, SDIN2, and SDIN3). When selected as an input to the SRC, this SDIN line is assumed to contain asynchronous data and is then masked as an input to the audio processor to ensure that asynchronous data is not processed as synchronous data. By default, SRC1 uses the LRCLK0 and BCLK0 as the clock and framing signals. The SRC2 is a 6-channel (3-stereo) sample rate converter that is capable of using any of the three serial clocks available. The SRC2 can accept data from any of the serial data inputs (SDIN0, SDIN1, SDIN2, and SDIN3). When selected as an input to the SRC, this SDIN line is assumed to contain asynchronous data and is then masked internally as an input to the audio processor to ensure that asynchronous data is not processed as synchronous data. By default, SRC2 uses the LRCLK2 and BCLK2 as the clock and framing signals. The first output (SRC2A) from SRC2 is always available to the audio processor. The other two outputs are muxed with two of the serial inputs before being available to the audio processor. SRC2B is muxed with SDIN2, and SRC2C is muxed with SDIN3. By default, these muxes are configured so that the synchronous inputs are available to the audio processor. The SRC2B and SRC2C channels can be made available to the audio processor simply by enabling them by register write. When using the ADAV4601 in an asynchronous digital-in-to- digital-out configuration, the input digital data is input to the audio processor core from one of the SRCs, using the assigned BCLK/LRCLK as a framing signal. The digital output is synchronous to the BCLK/LRCLK, which is assigned to the synchronous port; the default clock in this case is BCLK1 and LRCLK1. Serial Data Interface LRCLK is the framing signal for the left- and right-channel inputs, with a frequency equal to the sampling frequency (fS). BCLK is the bit clock for the digital interface, with a frequency of 64 × fS (32 BCLK periods for each of the left and right channels). The serial data interface supports all the popular audio interface standards, such as I2S, left-justified (LJ), and right-justified (RJ). The interface mode is software selectable, and its default is I2S. The data sample width is also software selectable from 16 bits, 20 bits, or 24 bits. The default is 24 bits. |
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