PIC16F877ATISLASHML datasheet(83/234 Pages) MICROCHIP

83 / 234 page

 2003 Microchip Technology Inc.

DS39582B-page 81

PIC16F87XA

SSPSTAT: MSSP STATUS REGISTER (I2C MODE) (ADDRESS 94h)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

bit 7

SMP: Slew Rate Control bit

In Master or Slave mode:

= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

= Slew rate control enabled for high-speed mode (400 kHz)

bit 6

CKE: SMBus Select bit

In Master or Slave mode:

= Enable SMBus specific inputs

= Disable SMBus specific inputs

bit 5

D/A: Data/Address bit

In Master mode:

Reserved.

In Slave mode:

= Indicates that the last byte received or transmitted was data

= Indicates that the last byte received or transmitted was address

bit 4

P: Stop bit

= Indicates that a Stop bit has been detected last

= Stop bit was not detected last

Note:

This bit is cleared on Reset and when SSPEN is cleared.

bit 3

S: Start bit

= Indicates that a Start bit has been detected last

= Start bit was not detected last

Note:

This bit is cleared on Reset and when SSPEN is cleared.

bit 2

R/W: Read/Write bit information (I2C mode only)

In Slave mode:

= Read

= Write

Note:

This bit holds the R/W bit information following the last address match. This bit is

only valid from the address match to the next Start bit, Stop bit or not ACK bit.

In Master mode:

= Transmit is in progress

= Transmit is not in progress

Note:

ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is

in Idle mode.

bit 1

UA: Update Address (10-bit Slave mode only)

= Indicates that the user needs to update the address in the SSPADD register

= Address does not need to be updated

bit 0

BF: Buffer Full Status bit

In Transmit mode:

= Receive complete, SSPBUF is full

= Receive not complete, SSPBUF is empty

In Receive mode:

= Data Transmit in progress (does not include the ACK and Stop bits), SSPBUF is full

= Data Transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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