数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

PIC16F877ATI/ML 数据表(PDF) 134 Page - Microchip Technology

部件名 PIC16F877ATI/ML
功能描述  28/40-pin Enhanced FLASH Microcontrollers
PDF  234 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

PIC16F877ATI/ML 数据表(HTML) 134 Page - Microchip Technology

Back Button PIC16F877ATI/ML Datasheet HTML 130Page - Microchip Technology PIC16F877ATI/ML Datasheet HTML 131Page - Microchip Technology PIC16F877ATI/ML Datasheet HTML 132Page - Microchip Technology PIC16F877ATI/ML Datasheet HTML 133Page - Microchip Technology PIC16F877ATI/ML Datasheet HTML 134Page - Microchip Technology PIC16F877ATI/ML Datasheet HTML 135Page - Microchip Technology PIC16F877ATI/ML Datasheet HTML 136Page - Microchip Technology PIC16F877ATI/ML Datasheet HTML 137Page - Microchip Technology PIC16F877ATI/ML Datasheet HTML 138Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 134 / 234 page
background image
PIC16F87XA
DS39582B-page 132
 2003 Microchip Technology Inc.
11.4
A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, the next acquisition on the selected channel
is automatically started. The GO/DONE bit can then be
set to start the conversion.
In Figure 11-3, after the GO bit is set, the first time
segment has a minimum of TCY and a maximum of TAD.
FIGURE 11-3:
A/D CONVERSION TAD CYCLES
11.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general
purpose 8-bit registers.
FIGURE 11-4:
A/D RESULT JUSTIFICATION
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
TAD9
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b9
b8
b7
b6
b5
b4
b3
b2
TAD10 TAD11
b1
b0
TCY to TAD
Conversion starts
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
10-bit Result
ADRESH
ADRESL
0000 00
ADFM = 0
0
2 1 0 7
7
10-bit Result
ADRESH
ADRESL
10-bit Result
0000 00
7
0 7 6 5
0
ADFM = 1
Right Justified
Left Justified



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com