COP888EB datasheet(47/75 Pages) NSC

47 / 75 page

Serial Peripheral Interface

The Serial Peripheral Interface (SPI) is used in master-slave

bus systems. It is a synchronous bidirectional serial commu-

nication interface with two data lines MISO and MOSI (Mas-

ter In Slave Out, Master Out Slave In). A serial clock and a

slave select (SS) signal are always generated by the SPI

Master. The interface receives/transmits protocol frames

with up to 12 bytes length within a frame, where a frame is

defined as the time between a falling edge and a rising edge

of SS.

THEORY OF OPERATION

Figure 38 shows a block diagram illustrating the basic opera-

tion of the SPI circuit. In the SPI interface, data is

transmitted/received in packets of 8 bits length which are

shifted into/out of a shift register with the active edge of the

shift clock SCK. Two 12 byte FIFOs, which serve as a re-

ceive and a transmit buffer, allow a maximum message

length of 12 x 8 bits in both transmit and receive direction

without CPU intervention. With CPU intervention, many

more bytes can be received. Two registers, the SPI Control

are used to control the SPI interface via the internal COP

bus. Several different operation modes, such as master or

slave operation, are possible.

An SS-Expander allows the generation of up to 8 signals on

the N-port, which can be used as additional SS-signals

(ESS[7:0]) or as host programmable general purpose sig-

nals. The SS-Expander is programmed with the content of

the first MOSI-byte (i.e., the content of the 1st byte [7:0] ap-

pears at ESS[7:0]) (N-port[7:0]), respectively), if the ESS

programming mode is selected. The ESS programming

mode is selected by the condition MOSI = L at the falling

edge of SS.

Use of the ESS expander requires the setup of four condi-

tions by the user.

Set the SESSEN bit of SPICNTL.

Set PORTNX to select which bits are used for SS expan-

sion.

Configure the PORTNC register to enable the desired

SS expansion bits as outputs.

Have an ESS condition (MOSI = low at the falling edge

of SS).

Loop Back Mode

Setting the SLOOP bit enables the Loop Back mode, which

can be used for test purposes. If the Loop Back mode is se-

lected, TX FIFO data are communicated to the RX FIFO via

the SPI Register. In the slave mode, MISO output is inter-

nally connected to the MOSI input. In the master mode, the

MOSI output is internally connected to the MISO input.

DS012837-38

FIGURE 36. SPI Transmission Example

DS012837-39

FIGURE 37. Loop Back Mode Block Diagram

COP888EB 数据表(PDF) 47 Page - National Semiconductor (TI)

COP888EB 数据表(HTML) 47 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

数据表下载