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Serial Peripheral Interface (Continued)

B[4:3]

SPIMOD[1:0]

SPI operation mode select

SPIMOD[1:0]

0 0: Slave mode,

— SCK is SPI clock input

— MISO is SPI data output

— MOSI is SPI data input

— SS is slave select input

1 0: Standard Master mode,

— SCK is SPI clock output (CKI/40)

— MISO is SPI data input

— MOSI is SPI data output

— SS is slave select output

In the Master mode, 3 different SPI clock frequencies are available:

01:f

SCK = 1/(tc) = CKI/10

10:f

SCK = 1/(4 tc) = CKI/40

11:f

SCK = 1/(16 tc) = CKI/160

SCE

SPI active clock edge select

0: data are shifted out on the falling edge of SCK and are shifted in on the rising edge of SCK

1: data are shifted out on the rising edge of SCK and are shifted in on the falling edge of SCK

SPIEN

SPI enable

Enables the SPI interface and the alternate functions of the MISO, MOSI, SCK and SS pins.

0: disable SPI

1: enable SPI, all Port M ESS signals are set to 1

SLOOP

SPI loop back mode

0: disable loop back mode

1: enable loop back mode, MISO and MOSI are internally connected (see

Figure 39)

PROGRAMMING THE SPI EXPANDER

If the SS Expander is enabled by setting SESSEN=1inthe

SPI Control Register (SPICNTL), the N-port will be pro-

grammed with the content of the first MOSI-byte (i.e., the

content of the 1st byte [7:0] appears at N-port[7:0] after com-

plete reception of the first byte), if the ESS programming

mode is detected. If any bytes follow after the 1st MOSI byte,

all data will be ignored by the SPI.

The ESS programming mode is detected by the ESS control

logic, which decodes the condition “MOSI = L at the falling

edge of SS. For further details, see

Figure 39.

The selected N-port bits will be set to 1 after the positive

edge of SS.

Single N-port bits may be enabled for use as SS expansion,

or disabled to allow for general purpose I/O, by the respec-

tive bits in the PORTNX register.

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