COP888EB datasheet(8/75 Pages) NSC

8 / 75 page

DC Electrical Characteristics COP68xEB (Continued)

Note 11: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at VCC or GND, and outputs open.

Note 12: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to VCC; Port C, G, E, F, L, M and N I/Os con-

figured as outputs and programmed low; D outputs programmed high. Parameter refers to HALT mode entered via setting bit 7 of the Port G data register. Part will

pull up CKI during HALT in crystal clock mode. Both CAN main comparator and the CAN Wakeup comparator need to be disabled.

Note 13: HALT and IDLE current specifications assume CAN block comparators are disabled.

Note 14: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than VCC and the pins will have isnk current

to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω

(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

Note 15: Condition and parameter valid only for part in HALT mode.

Note 16: Parameter characterized but not tested.

AC Electrical Characteristics COP68xEB and COP88xEB

−55˚C

≤ T

A ≤ +125˚C

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t

Crystal/Resonator

CC ≥ 4.5V

1.0

µs

Inputs

SETUP

CC ≥ 4.5V

200

HOLD

CC ≥ 4.5V

Output Propagation Delay (t

PD1,tPD0) (Note 19)

L = 100 pF, RL = 2.2 kΩ

SK, SO

CC ≥ 4.5V

0.7

µs

All others

CC ≥ 4.5V

µs

MICROWIRE

Setup Time (t

UWS) (Note 20)

Hold Time (t

UWH) (Note 20)

Output Pop Delay (t

UPD)

220

Input Pulse Width

Interrupt High Time

Interrupt Low Time

Timer 1, 2 High Time

Timer 1, 2 Low Time

Reset Pulse Width (Note 20)

1.0

µs

tc = Instruction Cycle Time

Note 17: The maximum bus speed achievable with the CAN interface is a function of crystal frequency, message length and software overhead. The device can sup-

port a bus speed of up to 1 Mbit/S with a 10 MHz oscillator and 2 byte messages. The 1M bus speed refers to the rate at which protocol and data bits are transferred

on the bus. Longer messages require slower bus speeds due to the time required for software intervention between data bytes. The device will support a maximum

of 125k bits/s with eight byte messages and a 10 MHz oscillator.

Note 18: For device testing purpose of all AC parameters, VOH will be tested at 0.5*VCC.

Note 19: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 20: Parameter not tested.

On-Chip Voltage Reference

−55˚C

≤ T

A ≤ +125˚C

Parameter

Conditions

Min

Max

Units

Reference Voltage

OUT < 80 µA,

0.5V

CC −0.12

0.5V

CC +0.12

REF

CC =5V

Reference Supply

OUT = 0A, (No Load)

120

µA

Current, I

CC = 5V (Note 21)

Note 21: Reference supply IDD is supplied for information purposes only, it is not tested.

COP888EB 数据表(PDF) 8 Page - National Semiconductor (TI)

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COP888EB 数据表(PDF) 8 Page - National Semiconductor (TI)

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