REV. B

AD1981B

–13–

MCV[4:0]

MIC Volume Gain. Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB

each. The LSB represents 1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, with the mute

bit enabled.

M20

MIC Gain Boost. This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal

gain boost by default is 20 dB; however, Bits D0 and D1 (MBG[1:0]) on the miscellaneous control bits register

(76h) allow changing the gain boost to 10 dB or 30 dB if necessary.

0 = Disabled; Gain = 0 dB

1 = Enabled; Default Gain = 20 dB (see Register 76h, Bits D0, D1)

MCM

MIC Mute. When this bit is set to 1, the MIC channel is muted.

Table III. Volume Settings for Phone and MIC

Control Bits D[4:0]

Phone (0Ch) and Mic (0Eh)

D15

WRITE

READBACK

Function

00 0000

0 0000

12 dB Gain

00 1000

0 1000

0 dB Gain

01 1111

1 1111

–34.5 dB Gain

1x xxxx

x xxxx

–

dB Gain, Muted

x in the above table is a wild card, and has no effect on the value.

RLV[4:0]

Line In Volume Right. Allows setting the line-in right channel attenuator in 32 volume levels. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

RM

Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the LM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.

LLV[4:0]

Line In Volume Left. Allows setting the line in left channel attenuator in 32 volume levels. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

LVM

Line In Mute. When this bit is set to 1, both the left and right channels are muted unless the MSPLT bit in

Register 76h is set to 1, in which case this mute bit will affect only the left channel.

Line-In Volume Register (Index 10h)

Reg

No. Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

10h Line-In Volume LVM

X

X

LLV4 LLV3

LLV2

LLV1

LLV0

RM

*

XX

RLV4

RLV3

RLV2

RLV1

RLV0

8808h

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.

MIC Volume Register (Index 0Eh)

Reg

No. Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0Eh MIC Volume

MCM

X

X

X

X

X

X

X

X

M20

X

MCV4

MCV3

MCV2

MCV1 MCV0 8008h

All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.