REV. B

AD1981B

–14–

RCV[4:0]

Right CD Volume. Allows setting the CD right channel attenuator in 32 volume levels. The LSB represents 1.5 dB,

and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

RM

Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the CVM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1.

LCV[4:0]

Left CD Volume. Allows setting the CD left channel attenuator in 32 volume levels. The LSB represents 1.5 dB,

and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

CVM

CD Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in

Register 76h is set to 1, in which case this mute bit will affect only the left channel.

RAV[4:0]

Right AUX Volume. Allows setting the AUX right channel attenuator in 32 volume levels. The LSB represents 1.5 dB,

and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

RM

Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the AM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1.

LAV[4:0]

Left AUX Volume. Allows setting the AUX left channel attenuator in 32 volume levels. The LSB represents 1.5 dB,

and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

AM

AUX Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in

Register 76h is set to 1, in which case this mute bit will affect only the left channel.

ROV[4:0]

Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

RM

Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the OM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.

LOV[4:0]

Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

OM

PCM Out Volume Mute. When this bit is set to 1, both the left and right channels are muted unless the MSPLT

bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.

AUX Volume Register (Index 16h)

Reg

No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

16h

AUX Volume

AM

X

X

LAV4 LAV3

LAV2

LAV1

LAV0

RM

*

XX

RAV4

RAV3

RAV2 RAV1 RAV0 8808h

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.

PCM-Out Volume Register (Index 18h)

Reg

No. Name

D15 D14 D13 D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

18h PCM-Out Volume OM X

X

LOV4 LOV3

LOV2

LOV1

LOV0

RM

*

XXROV4

ROV3 ROV2 ROV1 ROV0 8808h

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.

CD Volume Register (Index 12h)

Reg

No. Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

12h CD Volume

CVM

X

X

LCV4 LCV3

LCV2

LCV1 LCV0 RM

*

XX

RCV4

RCV3

RCV2

RCV1

RCV0

8808h

*For AC ’97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.