REV. B

AD1981B

–23–

JS0INT

Indicates Pin JS0 Has Generated an Interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR

should clear this bit by writing a 0 to it. Note that the interrupt to the system is actually an OR combination of

this bit and JS1INT. Also note that the actual interrupt implementation is selected by the INTS bit (Register 76h).

It is also possible to generate a software system interrupt by writing a 1 to this bit.

JS1INT

Indicates Pin JS1 Has Generated an Interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR

should clear this bit by writing a 0 to it. See JS0INT description for additional details.

JS0ST

JS0 State. This bit always reports the logic state of JS0 pin.

JS1ST

JS1 State. This bit always reports the logic state of JS1 pin.

JS0MD

JS0 Mode. This bit selects the operation mode for the JS0 pin.

0 = Jack Sense mode (default).

1 = Interrupt mode.

JS1MD

JS1 Mode. This bit selects the operation mode for the JS1 pin.

0 = Jack Sense mode (default).

1 = Interrupt mode.

JS0TMR

JS0 Timer Enable. If this bit is set to a 1, JS0 must be high for greater than 278 ms to be recognized.

JS1TMR

JS1 Timer Enable. If this bit is set to a 1, JS1 must be high for greater than 278 ms to be recognized.

JS0EQB

JS0 EQ Bypass Enable. This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 will

cause the EQ to be bypassed.

JS1EQB

JS1 EQ Bypass Enable. This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1 = 1 will

cause the EQ to be bypassed.

JSMT[2,0]

JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table VIII).

Jack Sense/Audio Interrupt/Status Register (Index 72h)

Reg

No. Name

D15 D14

D13 D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

72h Jack Sense

X

X

X

JS

JS

JS

JS1

JS0

JS1

JS0

JS1

JS0

JS1

JS0

JS1

JS0

0000h

MT2

MT1

MT0

EQB

EQB

TMR

TMR

MD

MD

ST

ST

INT

INT

All register bits are read/write except for JS0ST and JS1ST, which are read only. All registers not shown and bits containing an X are assumed to be reserved.