数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

CC1050-RTR1 数据表(PDF) 14 Page - Texas Instruments

Click here to check the latest version.
部件名 CC1050-RTR1
功能描述  Single Chip Very Low Power RF Transmitter
PDF  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CC1050-RTR1 数据表(HTML) 14 Page - Texas Instruments

Back Button CC1050-RTR1 Datasheet HTML 10Page - Texas Instruments CC1050-RTR1 Datasheet HTML 11Page - Texas Instruments CC1050-RTR1 Datasheet HTML 12Page - Texas Instruments CC1050-RTR1 Datasheet HTML 13Page - Texas Instruments CC1050-RTR1 Datasheet HTML 14Page - Texas Instruments CC1050-RTR1 Datasheet HTML 15Page - Texas Instruments CC1050-RTR1 Datasheet HTML 16Page - Texas Instruments CC1050-RTR1 Datasheet HTML 17Page - Texas Instruments CC1050-RTR1 Datasheet HTML 18Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 14 / 40 page
background image
CC1050
SWRS044
Page 14 of 40
Microcontroller Interface
Used in a typical system,
CC1050 will
interface
to
a
microcontroller.
This
microcontroller must be able to:
•
Program
CC1050 into different modes
via the 3-wire serial configuration
interface (PDATA, PCLK and PALE).
•
Interface to the synchronous data
signal interface (DI and DCLK).
•
Optionally the microcontroller can do
data encoding / decoding.
•
Optionally the microcontroller can
monitor the frequency lock status from
pin CHP_OUT (LOCK).
Connecting the microcontroller
The microcontroller uses 3 output pins for
the configuration interface (PDATA, PCLK
and PALE). PDATA should be a bi-
directional pin for data read-back. The DI
pin is used for data to be transmitted.
DCLK providing the data timing should be
connected to a microcontroller input.
Optionally another pin can be used to
monitor the LOCK signal (available at the
CHP_OUT pin). This signal is logic level
high when the PLL is in lock. See
Figure 6.
The microcontroller pins connected to
PDATA and PCLK can be used for other
purposes when the configuration interface
is not used. PDATA and PCLK are high
impedance inputs as long as PALE high.
PALE has an internal pull-up resistor and
should be left open (tri-stated by the
microcontroller) or set to a high level
during power down mode in order to
prevent a trickle current flowing in the pull-
up.
CC1050
PDATA
PCLK
PALE
DI
CHP_OUT
(LOCK)
Micro-
controller
DCLK
(Optional)
CC1050
PDATA
PCLK
PALE
DI
CHP_OUT
(LOCK)
Micro-
controller
DCLK
(Optional)
Figure 6. Microcontroller interface
Not Recommended for New Designs



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com