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数据搜索系统，热门电子元器件搜索 |
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CC2400-RTR1 数据表(PDF) 22 Page - Texas Instruments |
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CC2400-RTR1 数据表(HTML) 22 Page - Texas Instruments |
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22 / 84 page  CC2400 SWRS042A Page 22 of 83 0 A6 A5 A4 A3 A2 A0 A1 D W15 DW14 DW13 D W12 D W11 DW10 D W9 D W8 D W7 D W6 D W5 D W4 D W3 D W2 D W1 D W0 S7 S6 S5 S4 S3 S2 S0 S1 1 A6 A5 A4 A3 A2 A0 A1 D R15 D R14 D R13 D R12 D R11 D R10 D R9 D R8 D R7 D R6 D R5 D R4 D R3 D R2 D R1 D R0 S7 S6 S5 S4 S3 S2 S0 S1 Read from register: Write to register: X X X X X t sp t ch t sd t ns D R15 t hd SCLK: CSn: SI SO SI SO t ps t cl Figure 6. SPI timing diagram ADDR CSn: Command strobe: Read or write a whole register (16 bit): DATA 8MSB ADDR DATA 8LSB Read or write 8 MSB of a register: DATA 8MSB ADDR Read or write a whole register continuously: DATA 8MSB ADDR DATA 8LSB DATA 8MSB DATA 8LSB DATA 8MSB DATA 8LSB ... Read or write n bytes from/to RF FIFO: DATA byte0 ADDR FIFO DATA byte1 DATA byte2 DATA byte3 DATA byte n-2 DATAbyte n-1 ... Figure 7. Configuration registers write and read operations via SPI Parameter Symbol Min Max Units Conditions SCLK, clock frequency fSCLK 20 MHz SCLK low pulse duration tcl,min 25 ns The minimum time SCLK must be low. SCLK high pulse duration tch,min 25 ns The minimum time SCLK must be high. CSn setup time tsp 25 ns The minimum time CSn must be low before positive edge of SCLK. CSn hold time 1 tns 25 ns The minimum time CSn must be held low after the last negative edge of SCLK. CSn hold time 2 tps 300 ns In buffered mode: The minimum time CSn must be held low after the last positive edge of SCLK. This only applies to FIFO accesses. SI setup time tsd 25 ns The minimum time data on SI must be ready before the positive edge of SCLK. SI hold time thd 25 ns The minimum time data must be held at SI, after the positive edge of SCLK. Rise time trise 100 ns The maximum rise time for SCLK and CSN Fall time tfall 100 ns The maximum fall time for SCLK and CSn Note: The set-up- and hold-times refer to 50% of VDD. Table 12. SPI timing specification |
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