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CC2400-RTR1 数据表(PDF) 12 Page - Texas Instruments |
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CC2400-RTR1 数据表(HTML) 12 Page - Texas Instruments |
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12 / 84 page ![]() CC2400 SWRS042A Page 12 of 83 Parameter Min. Typ. Max. Unit Condition / Note PLL lock time (RX / TX turn-on time) 40 µs Until within ± 10 kHz Step size is 1MHz, no calibration. Note: Calibration should be performed for frequency changes > 8 MHz. PLL turn-on time from IDLE mode, crystal oscillator on 100 µs Crystal oscillator running. Calibration time included. Table 8 Frequency synthesizer characteristics 13 Digital Inputs/Outputs Parameter Min. Typ. Max. Unit Condition / Note Signal levels are referred to the voltage level at the pin DVDD3.3. Logic "0" input voltage 0 0.3* DVDD V Logic "1" input voltage 0.7* DVDD DVDD V Logic "0" output voltage 0 0.4 V Output current −8 mA, 3.3 V supply voltage Logic "1" output voltage 2.5 DVDD V Output current 8 mA, 3.3 V supply voltage Logic "0" input current NA −1 µA Input signal equals GND Logic "1" input current NA 1 µA Input signal equals DVDD DIO setup time 20 ns TX un-buffered mode, minimum time DIO must be ready before the positive edge of DCLK DIO hold time 10 ns TX un-buffered mode, minimum time DIO must be held after the positive edge of DCLK Serial interface (SCLK, SI, SO and CSn) timing specification See Table 12 page 22 Table 9 Digital input/output characteristics |
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