DAC5686IPZP datasheet(45/53 Pages) TI1

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DAC Transfer Function

Reference Operation

IOUT

FS +

EXTIO

BIAS

DAC5686

www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009

The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output

current up to 20 mA. Differential current switches direct the current of each current source through either one of

the complementary output nodes IOUT1 or IOUT2. Complementary output currents enable differential operation,

thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even

order distortion components, and increasing signal output power by a factor of two.

The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage

reference source (1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to provide

a full-scale output current equal to 16 times IBIAS. The full-scale current IOUTFS can be adjusted from 20 mA

down to 2 mA.

The relation between IOUT1 and IOUT2 can be expressed as:

IOUT1 = –IOUTFS – IOUT2

We denote current flowing into a node as – current and current flowing out of a node as + current. Because the

output stage is a current sink, the current can only flow from AVDD into the IOUT1 and IOUT2 pins. If IOUT2 =

–5 mA and IO(FS) = 20 mA then:

IOUT1 = –20 – (–5) = –15 mA

The output current flow in each pin driving a resistive load can be expressed as:

IOUT1 = IOUTFS × (65535 – CODE) / 65536

IOUT2 = IOUTFS × CODE / 65536

where CODE is the decimal representation of the DAC data input word.

For the case where IOUT1 and IOUT2 drive resistor loads RL directly, this translates into single ended voltages

at IOUT1 and IOUT2:

VOUT1 = AVDD – I IOUT1 I × RL

VOUT2 = AVDD – I IOUT2 I × RL

Assuming that the data is full scale (65535 in offset binary notation) and the RL is 25 Ω, the differential voltage

between pins IOUT1 and IOUT2 can be expressed as:

VOUT1 = AVDD – I -20 mA I x 25

Ω = 2.8 V

VOUT2 = AVDD – I -0 mA I x 25

Ω = 3.3 V

VDIFF = VOUT1 – VOUT2 = 0.5 V

Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would

lead to increased signal distortion.

The DAC5686 comprises a band-gap reference and control amplifier for biasing the full-scale output current. The

full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS

is defined by the on-chip band-gap reference voltage and control amplifier. The full-scale output current equals

16 times this bias current. The full-scale output current IOUTFS can thus be expressed as (coarse gain = 15, fine

gain = 0):

where VEXTIO is the voltage at terminal EXTIO. The band-gap reference voltage delivers an accurate voltage of

1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor

CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The band-gap reference

additionally can be used for external reference operation. In that case, an external buffer with a high-impedance

input should be used in order to limit the band-gap load current to a maximum of 100 nA. The internal reference

can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may

hence be omitted. Terminal EXTIO serves as either input or output node.

The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing the

externally applied reference voltage. The internal control amplifier has a wide input range supporting the

full-scale output current range of 20 dB.

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