ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS)

(1)

DAC5686

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

16

INL

Integral nonlinearity

12

LSB

1.84e–4

DNL

Differential nonlinearity

9

LSB

1.37e–4

Analog Output

Coarse gain linearity (INL)

0.016

LSB

Fine gain linearity (INL)

3

LSB

Offset error

Mid-code offset

0.003

%FSR

Without internal reference

0.7

Gain error

%FSR

With internal reference

0.7

Gain mismatch

With internal reference, dual DAC,

–2

2

%FSR

SSB mode

2

20

mA

AVDD – 0.5

AVDD + 0.5

V

Output resistance

300

k

Ω

Output capacitance

5

pF

Reference Output

Reference voltage

1.14

1.2

1.26

V

100

nA

Reference Input

Input voltage range

0.1

1.25

V

Input resistance

1

M

Ω

Small-signal bandwidth

2.5

kHz

Input capacitance

100

pF

Temperature Coefficients

ppm of

Offset drift

3

FSR/C

Without internal reference

15

ppm of

Gain drift

FSR/C

With internal reference

40

Reference voltage drift

25

ppm/C

(1)

Specifications subject to change without notice.

(2)

Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25

Ω each to AVDD

(3)

(4)

The upper limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,

resulting in reduced reliability of the DAC5686 device. The lower limit of the output compliance is determined by the load resistors and

full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(5)

Use an external buffer amplifier with high-impedance input to drive any external load.

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