AD8555ACP-R2 datasheet(25/28 Pages) AD

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AD8555

Rev. 0 | Page 25 of 28

FILTERING FUNCTION

The AD8555’s FILT/DIGOUT pin can be used to create a simple

low-pass filter. The AD8555’s internal 18 kΩ resistor can be

used with an external capacitor for this purpose. Typical

responses of the AD8555, configured for a gain of 70 and gain

of 1280, are shown in Figure 54 and Figure 55, respectively. This

filtering feature can be used to pass the signals within the filter’s

pass band while limiting the out-of-band signals bandwidth

and, therefore, reducing the noise of the overall solution.

AD8555

VDD

FILT/DIGOUT

DIGIN

VNEG

VSS

VOUT

VCLAMP

VPOS

VOUT

VDD

CFILTER

VDD

VSS

VIN

Figure 53. AD8555 Configured to Filter Noise

100

10k

50k

CFILTER = 0.001µF

CFILTER = 0.010µF

CFILTER = 0.100µF

Figure 54. Typical Response of the AD8555 at FILT/DIGOUT Pin (Gain = 70)

100k

100

10k

CFILTER = 0.001µF

CFILTER = 0.010µF

CFILTER = 0.100µF

Figure 55. Typical Response of the AD8555 at FILT/DIGOUT Pin (Gain = 1280)

DRIVING CAPACITIVE LOADS

The AD8555 can drive large capacitive loads. This feature is

useful when the amplifier, placed close to the sensor, has to

drive long cables. Most instrumentation amplifiers have diffi-

culty driving capacitance due to the degradation of the phase

margin caused by the additional phase lag from the capacitive

load. Higher capacitance at the output can increase the amount

of overshoot and ringing in the amplifier’s step response and

could even affect the stability of the device. Additionally, the

value of the capacitive load that an amplifier can drive before

oscillation varies with gain, supply voltage, input signal, and

temperature. Figure 57 and Figure 58 show the overshoot

response of AD8555 versus the capacitive load with a different

value isolation resistor (RS) in Figure 56. Similar to all amplifi-

ers, the AD8555 responds with overshoot when driving large CL,

but after a point (approximately 22 nF), the overshoot decreases.

This is because the pole created by CL dominates at first; how-

ever, at some point, the pole is farther in than the pole setting of

the buffer amplifier and is ignored by AD8555.

AD8555

VDD

FILT/DIGOUT

DIGIN

VNEG

VSS

VOUT

VCLAMP

VPOS

VDD

VOUT

VSS

CFILTER

Figure 56. Test Circuit for Driving Capacitive Loads

LOAD CAPACITANCE (nF)

100

0.1

CL = 1nF

OUTPUT

BUFFER

VS = ±2.5V

RS = 0

RS = 10

RS = 20

RS = 50

RS = 100

Figure 57. Positive Overshoot Graph vs. CL

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