BQ78350-R1 datasheet(8/32 Pages) TI1

8 / 32 page

bq78350-R1

SLUSCD0 – AUGUST 2015

www.ti.com

SMBus Timing Specifications (continued)

VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Hold time after

tHD:STA

µs

(repeated) start

Repeated start setup

tSU:STA

4.7

µs

time

tSU:STO

Stop setup time

µs

RECEIVE mode

tHD:DAT

Data hold time

TRANSMIT mode

300

tSU:DAT

Data setup time

250

tTIMEOUT

Error signal/detect

See note(1)

tLOW

Clock low period

4.7

µs

tHIGH

Clock high period

See note(2)

Cumulative clock low

tLOW:SEXT

See note(3)

slave extend time

Cumulative clock low

tLOW:MEXT

See note(4)

master extend time

Clock/data fall time

(VILMAX – 0.15 V) to (VIHMIN + 0.15 V)

300

Clock/data rise time

0.9 VCC to (VILMAX – 0.15 V)

1000

(1)

The bq78350-R1 times out when any clock low exceeds tTIMEOUT.

(2)

tHIGH:MAX is minimum bus idle time. SMBC = 1 for t > 50 μs causes a reset of any transaction in progress involving the bq78350-R1.

(3)

tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to stop.

(4)

tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to stop.

Figure 1. SMBus Timing Diagram

Submit Documentation Feedback

Product Folder Links: bq78350-R1

BQ78350-R1 数据表(PDF) 8 Page - Texas Instruments

BQ78350-R1 数据表(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载