ADE3700XT datasheet(80/89 Pages) STMICROELECTRONICS

80 / 89 page

Pulse Width Modulation (PWM)

ADE3700

80/89

2.20

Pulse Width Modulation (PWM)

The PWM block generates two signals that can be used to control backlight inverter switching

power components directly. It is derived from XCLK and can be powered up independently of the

DOTCLK and INCLK domains. The frequency, duty cycle, polarity and overlap/non-overlap are

programmable. The output frequency can be free-running or locked to the output vsync signal.

OMUX_CTRL_3

0x0C51

R/W

[7:3]

Reserved

R/W

[2]

0x0

PWM mux mode

R/W

[1]

0x0

PWM enable

R/W

[0]

0x0

TCON data invert enable, with computed

data invert pin.

OMUX_REFCOUNT

0x0C52

[7:6]

Reserved

[5:0]

0x0

Returns a value that indicates the ADE

gate speed -- a function of temp and

voltage

higher = faster logic

Table 33: PWM Registers (Sheet 1 of 2)

Addr

Mode

Bits

Default

Description

PWM_CTRL0

0x01A0

[7]

0x0

PWM status

0: unlocked

1: locked

R/W

[6]

0x0

0: lock to CYCLES_PER_FRAME from the

free-running state machine

1: lock to CYCLES_PER_FRAME register

setting

R/W

[5]

0x0

PWM_A polarity

0: active low

1: active high

R/W

[4]

0x0

PWM_B polarity

0: active low

1: active high

R/W

[3]

0x0

0: normal operation

1: force PWM outputs to polarity settings

R/W

[2]

0x0

0: change period or duty cycle at the end of

the current cycle

1: smooth change, period or duty cycle

increment/decrement every

PWM_STEP_DELAY cycle

R/W

[1]

0x0

0: free-running

1: lock to out_vsync

R/W

[0]

0x0

0: disable PWM output

1: enable PWM output

Table 32: Output Mux Registers (Sheet 4 of 4)

Addr

Mode

Bits

Default

Description

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