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ADE3700XT 数据表(PDF) 36 Page - STMicroelectronics |
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ADE3700XT 数据表(HTML) 36 Page - STMicroelectronics |
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36 / 89 page  Sync Multiplexer (SMUX) ADE3700 36/89 SMUX_CTRL3 0x0203 R [7:6] venab pending state 0x0: idle 0x1: venab pending frame 1 0x2: venab pending frame 2 Wait until 0 to write venab again if in henab or venab shadow mode. R [5] henab pending [4] Reserved R/W [3:2] 0x0 vtrigger reference 2’bx0: trigger ref = venab 2’b01: last pixel w/ anti-glitch 2’b11: first pixel w/ anti-glitch Anti-glitch modes work only with venab shadow mode. First/last pixel must be consistent with out_seq in this mode. R/W [1:0] 0x0 0x0: no shadow 0x1: simple shadow. When henab_rst_u is written, henab_set_l, henab_set_u, henab_rst_l take effect. When venab_rst_u is written, venab_set_l, venab_set_u, venab_rst_l take effect. 0x2: henab shadow. Wait for next available blank period to update positions after henab_rst_u or venab_rst_u is written. 0x3: venab shadow. Wait for next available vblank period to update positions after henab_rst_u or venab_rst_u is written. Venab update takes two frames. State can be watched in ctrl3[7:5]. SMUX_CLAMP_SET_L 0x0204 R/W [7:0] 0x0 ADC clamp signal rising edge [11:0], relative to selected H reference signal, in INCLKS (pixels) SMUX_CLAMP_SET_U 0x0205 R/W [3:0] 0x0 ADC clamp signal MSBs SMUX_CLAMP_RST_L 0x0206 R/W [7:0] 0x0 ADC clamp falling edge SMUX_CLAMP_RST_U 0x0207 R/W [3:0] 0x0 ADC clamp falling edge SMUX_HENAB_SET_L 0x0208 R/W [7:0] 0x0 Horizontal enable start [11:0] (left edge of image) relative to the selected H reference edge in INCLKS (pixels) HENAB _SET_U 0x0209 R/W [3:0] 0x0 horizontal enable start MSBs HENAB _RST_L 0x020A R/W [7:0] 0x00 horizontal enable end LSBs HENAB _RST_U 0x020B R/W [3:0] 0x0 horizontal enable end MSBs VENAB_SET_L 0x020C R/W [7:0] 0x00 vertical enable start (top edge of image) relative to the selected vertical reference edge in lines VENAB _SET_U 0x020D R/W [3:0] 0x0 vertical enable start MSBs VENAB _RST_L 0x020E R/W [7:0] 0x00 vertical enable end LSBs VENAB _RST_U 0x020F R/W [3:0] 0x0 vertical enable end MSBs Table 11: Sync Multiplexer Registers (Sheet 3 of 4) Register Name Addr Mode Bits Default Description |
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