数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADE3700XT 数据表(PDF) 24 Page - STMicroelectronics

部件名 ADE3700XT
功能描述  Analog LCD Display Engine for XGA and SXGA Resolutions
PDF  89 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3700XT 数据表(HTML) 24 Page - STMicroelectronics

Back Button ADE3700XT Datasheet HTML 20Page - STMicroelectronics ADE3700XT Datasheet HTML 21Page - STMicroelectronics ADE3700XT Datasheet HTML 22Page - STMicroelectronics ADE3700XT Datasheet HTML 23Page - STMicroelectronics ADE3700XT Datasheet HTML 24Page - STMicroelectronics ADE3700XT Datasheet HTML 25Page - STMicroelectronics ADE3700XT Datasheet HTML 26Page - STMicroelectronics ADE3700XT Datasheet HTML 27Page - STMicroelectronics ADE3700XT Datasheet HTML 28Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 89 page
background image
Sync Retiming (SRT)
ADE3700
24/89
SRTXK_COAST_VS_SEL
0x01E8
[7:4]
0x0
Reserved
R/W
[3]
0x0
coast signal trigger edge
0: posedge of selected vertical
1: negedge of selected vertical
R/W
[2:0]
0x0
source select for coast vert sync trigger
0x0: avsync pin
0x1: vsync from ahsync pin
0x2: vsync from acsync pin
0x3: Reserved
0x4: nc
0x5: nc
0x6: srt vsync (filtered vsync)
0x7: Reserved
SRTXK_COAST_RISE_L
0x01E9
R/W
[7:0]
0x0
rising edge of coast, in XCLKs from vsync
trigger
SRTXK_COAST_RISE_M
0x01EA
R/W
[7:0]
0x0
SRTXK_COAST_RISE_H
0x01EB
R/W
[7:0]
0x0
SRTXK_COAST_FALL_L
0x01EC
R/W
[7:0]
0x0
falling edge of coast, in XCLKs from vsync
trigger
SRTXK_COAST_FALL_M
0x01ED
R/W
[7:0]
0x0
SRTXK_COAST_FALL_H
0x01EE
R/W
[7:0]
0x0
SRTIK_HS_CTRL
0x01F0
[7:3]
0x0
Reserved
R/W
[2]
0x0
Resample clock edge to transfer hsync into
the INCLK domain; depends on LLK phase
offset value.
0: posedge INCLK
1: negedge INCLK
R/W
[1:0]
0x0
horz sync source select for resampling into
the INCLK domain
0x0: LLPLL lock sync (normal)
0x1: ahsync pin
0x2: acsync pin
0x3: Reserved
SRTIK_VS_SEL
0x01F1
[7:2]
0x0
Reserved
R/W
[1:0]
0x0
vert sync source select for resampling
0x0: avsync pin
0x1: vsync from ahsync pin
0x2: vsync from acsync pin
0x3: srt vsync (filtered vsync)
Table 8: Sync Retiming Registers (Sheet 2 of 2)
Register Name
Addr
Mode
Bits
Default
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com