POWER FAIL INTERRUPTS DESCRIPTION

The Power Fail Status Flag in the Main Status Register

monitors the state of the internal power fail signal This flag

may be interrogated by the mP but it cannot be cleared it is

cleared automatically by the RTC when system power is

restored To generate an interrupt when the power fails the

Power Fail Interrupt Enable bit in Interrupt Control Register

1 is set Although this interrupt may not be cleared it may

be masked by clearing the Power Fail Interrupt Enable bit

POWER FAILURE CIRCUITRY FUNCTIONAL

DESCRIPTION

Since the clock must be operated from a battery when the

main system supply has been turned off the DP8573A pro-

vides circuitry to simplify design in battery backed systems

This switches over to the back up supply and isolates itself

from the host system

Figure 6 shows a simplified block

diagram of this circuitry which consists of three major sec-

tions 1) power loss logic 2) battery switch over logic and 3)

isolation logic

Detection of power loss occurs when PFAIL is low De-

bounce logic provides a 30 ms–63 ms debounce time which

will prevent noise on the PFAIL pin from being interpreted

as a system failure After 30 ms–63 ms the debounce logic

times out and a signal is generated indicating that system

power is marginal and is failing The Power Fail Interrupt will

then be generated

If chip select is low when a power failure is detected a

safety circuit will ensure that if a read or write is held active

continuously for greater than 30 ms after the power fail sig-

nal is asserted the lock-out will be forced

The battery switch over circuitry is completely independent

disconnected and the device is now in the standby mode If

indeterminate operation of the battery switch over circuit is

After the generation of a lock-out signal and eventual

switch in of the battery supply the pins of the RTC will be

configured as shown in Table II Outputs that have a pull-up

resistor should be connected to a voltage no greater than

TABLE II Pin Isolation during a Power Failure

Pin

Standby Mode

Logic 0

CS RD WR

Locked Out

Locked Out

A0 – A4

Locked Out

Locked Out

D0 – D7

Locked Out

Locked Out

Oscillator

Not Isolated

Not Isolated

PFAIL

Not Isolated

Not Isolated

INTR MFO

Not Isolated

Open Drain

The Interrupt Power Fail Operation bit in the Real-Time

Mode Register determines whether or not the interrupts will

continue to function after a power fail event

As power returns to the system the battery switch over cir-

greater than the battery voltage The chip will remain in the

chip is unlocked but only after another 30 ms min

m

s max debounce time The system designer must ensure

that his system is stable when power has returned

The power fail circuitry contains active linear circuitry that

undesirable so this circuit can be disabled by masking the

power fail interrupt The power fail input can perform all

lock-out functions previously mentioned except that no ex-

TLF9981 – 11

FIGURE 6 System-Battery Switchover (Upper Left) Power Fail

and Lock-Out Circuits (Lower Right)

9