Control and Status Register Address Bit Map

D7

D6

D5

D4

D3

D2

D1

D0

1 Reset by

Main Status Register

writing

RW

RW

RW

RW

1 to bit

RAM

Register

RAM

RAM

Alarm

Periodic

Power Fail

Interrupt

2 Setreset by

Select

Interrupt

Interrupt

Interrupt

Status

voltage at

PFAIL pin

3 Reset when

all pending

interrupts

are removed

Periodic Flag Register

4 Read Osc fail

RW

Write 0 Batt-

Test

Osc Fail

1 ms

10 ms

100 ms

Seconds

10 Second

Minute

Backed Mode

Mode

Single Supply

Flag

Flag

Flag

Flag

Flag

Flag

Write 1 Single

Supply Mode

5 Reset by

positive edge

of read

Time Save Control Register

Time Save

NA

RAM

RAM

RAM

RAM

RAM

RAM

All Bits RW

Enable

Real Time Mode Register

RAM

RAM

RAM

Interrupt EN

Clock

1224 Hr

Leap Year

Leap Year

All Bits RW

on Back-Up

StartStop

Mode

MSB

LSB

Output Mode Register

MFO as

RAM

RAM

RAM

RAM

RAM

RAM

RAM

All Bits RW

Crystal

Interrupt Control Register 0

1 ms

10 ms

100 ms

Seconds

10 Second

Minute

RAM

RAM

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

All Bits RW

Enable

Enable

Enable

Enable

Enable

Enable

Interrupt Control Register 1

Power Fail

Alarm

DOW

Month

DOM

Hours

Minute

Second

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

All Bits RW

Enable

Enable

Enable

Enable

Enable

Enable

Enable

Enable

Application Hints

Suggested Initialization Procedure for DP8573A in Bat-

1

Enter the test mode by writinga1tobit D7 in the Period-

ic Flag Register

2

Write zero to the RAMTEST mode Register located in

page 0 address HEX 1F

3

Leave the test mode by writinga0tobit D7 in the Peri-

odic Flag Register Steps 1 2 3 guarantee that if the

test mode had been entered during power on (due to

random pulses from the system) all test mode condi-

tions are cleared Most important is that the OSC Fail

Disable bit is cleared Refer to AN-589 for more informa-

tion on test mode operation

4

Enter a software loop that does the following

Set a 3 second(approx) software counter The crystal

oscillator may take 1 second to start

41 Writea1tobit D3 in the Real Time Mode Register (try

to start the clock) Under normal operation this bit can

be set only if the oscillator is running During the soft-

ware loop RAM real time counters output configura-

tion interrupt control and timer functions may be initial-

ized

13