LP3907TL-JSXSSLASHNOPB datasheet(18/58 Pages) TI1

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VIN

ENLDO

VLDO

GND

VREF

LDO

controlled

LP3907

SNVS511S – JUNE 2007 – REVISED APRIL 2016

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8.3 Feature Description

8.3.1 DC-DC Converters

8.3.1.1 Linear Low Dropout Regulators (LDOs)

LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.

LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control

programmed during final test, which can be tailored to the specific needs of the system designer.

Figure 30. LDO Block Diagram

8.3.1.2 No-Load Stability

The LDOs remain stable and in regulation with no external load. This is an important consideration in some

circuits, for example, CMOS RAM keep-alive applications.

8.3.1.3 LDO and LDO2 Control Registers

LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is

programmable in steps of 100 mV from 1 V to 3.5 V by programming bits D4-D0 in the LDO Control registers.

Both LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control

is also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in

the register is logic 1 by default. The output voltage can be altered while the LDO is enabled.

8.3.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters

8.3.2.1 Functional Description

The LP3907 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver

a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode

architecture with synchronous rectification, both bucks have the ability to deliver up to 1000 mA and 600 mA,

respectively, depending on the input voltage and output voltage (voltage headroom), and the inductor chosen

(maximum current capability).

There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode

handles current loads of approximately 70 mA or higher, delivering voltage precision of ±3% with 90% efficiency

or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current

consumption (IQ = 15 µA typical) and a longer battery life. The standby operating mode turns off the device,

offering the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be

forced through the setting of the buck control register.

Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of

the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage.

Additional features include soft-start, undervoltage lockout, current overload protection, and thermal overload

protection.

LP3907TL-JSXS/NOPB 数据表(PDF) 18 Page - Texas Instruments

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