LP3907TL-JSXSSLASHNOPB datasheet(31/58 Pages) TI1

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LP3907

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SNVS511S – JUNE 2007 – REVISED APRIL 2016

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8.6.1.3 EN_DLY Preset Delay Sequence After EN_T Assertion

EN_DLY<2:0>

DELAY (ms)

BUCK1

BUCK2

LDO1

LDO2

000

001

1.5

010

1.5

011

1.5

100

1.5

101

1.5

110

1.5

111

8.6.1.4 Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10

This register controls the enables for the Bucks and LDOs.

Name

—

LDO2EN

—

LDO1EN

—

BK2EN

—

BK1EN

Access

—

R/W

—

R/W

—

R/W

—

R/W

Data

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reset

8.6.1.5 Buck and LDO Status Register (BKLDOSR) – 0x11

This register monitors whether the Bucks and LDOs meet the voltage output specifications.

Name

BKS_OK

LDOS_OK

LDO2_OK

LDO1_OK

—

BK2_OK

—

BK1_OK

Access

—

Data

0 – Buck 1-2

Not Valid

1 – Bucks Valid

0 – LDO 1-2

Not Valid

1 – LDOs Valid

0 – LDO2 Not

Valid

1 – LDO2 Valid

0 – LDO1 Not

Valid

1 – LDO1 Valid

Reserve

0 – Buck2 Not

Valid

1 – Buck2 Valid

Reserve

0 – Buck1 Not

Valid

1 – Buck1 Valid

Reset

8.6.1.6 Buck Voltage Change Control Register 1 (VCCR) – 0x20

This register selects and controls the output target voltages for the buck regulators.

D7-6

D3-2

Name

—

B2VS

B2GO

—

B1VS

B1GO

Access

—

R/W

—

R/W

Data

Reserved

Buck2 Target Voltage

Select

0 – B2VT1

1 – B2VT2

Buck2 Voltage Ramp

CTRL

0 – Hold

1 – Ramp to B2VS

selection

Reserved

Buck1 Target Voltage

Select

0 – B1VT1

1 – B1VT2

Buck1 Voltage Ramp

CTRL

0 – Hold

1 – Ramp to B1VS

selection

Reset

LP3907TL-JSXS/NOPB 数据表(PDF) 31 Page - Texas Instruments

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LP3907TL-JSXS/NOPB 数据表(PDF) 31 Page - Texas Instruments

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