LP3907TL-JSXSSLASHNOPB datasheet(8/58 Pages) TI1

8 / 58 page

LP3907

SNVS511S – JUNE 2007 – REVISED APRIL 2016

www.ti.com

Product Folder Links: LP3907

Submit Documentation Feedback

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Minimum (MIN) and maximum (MAX) limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do

represent the most likely norm.

(3)

CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4)

The device maintains a stable, regulated output voltage without a load.

(5)

Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its

nominal value.

(6)

Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

(7)

VIN minimum for line regulation values is 1.8 V.

(8)

Pins 24, 19 can operate from VIN min of 1.74 V to a VIN max of 5.5 V. This rating is only for the series pass PMOS power FET. It allows

the system design to use a lower voltage rating if the input voltage comes from a buck output.

(9)

Limits apply over the entire junction temperature range for operation,

−40°C to +125°C.

(10) The IQ can be defined as the standing current of the LP3907 when the I

2C bus is active and all other power blocks have been disabled

via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3907 is powered using a battery.

(11) The IQ exhibits a higher current draw when the EN pin is de-asserted because the I

2C buffer pins draw an additional 2 µA.

7.6

Low Dropout Regulators, LDO1 And LDO2

Unless otherwise noted, VIN = 3.6 V, CIN = 1 µF, COUT = 0.47 µF, and TJ = 25°C.

(1) (2) (3) (4) (5) (6) (7)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN

Operational voltage range

VINLDO1 and VINLDO2 PMOS pins(8)

1.74(9)

5.5(9)

VOUT Accuracy Output voltage accuracy (default

VOUT)

Load current = 1 mA

–3%(9)

3%(9)

ΔVOUT

Line regulation

VIN = (VOUT + 0.3 V) to 5 V,

(7), load current = 1 mA

0.15(9)

%/V

Load regulation

VIN = 3.6 V,

Load current = 1 mA to IMAX

0.011(9)

%/mA

ISC

Short circuit current limit

LDO1-2, VOUT = 0 V

500

VIN – VOUT

Dropout voltage

Load current = 50 mA

(5)

200(9)

PSRR

Power supply ripple rejection

ƒ = 10 kHz, load current = IMAX

Supply output noise

10 Hz < F < 100 KHz

µVrms

(6) (10)

Quiescent current on

IOUT = 0 mA

µA

Quiescent current on

IOUT = IMAX

µA

Quiescent current off

EN is de-asserted(11)

0.03

µA

TON

Turnon time

Start-up from shutdown

300

µs

COUT

Output capacitor

Capacitance for stability

0°C

≤ TJ ≤ 125°C

0.33(9)

0.47

µF

−40°C ≤ TJ ≤ 125°C

0.68

µF

ESR

5(9)

500(9)

Ω

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Minimum (Min) and Maximum (Max) limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do

represent the most likely norm.

(3)

CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4)

The device maintains a stable, regulated output voltage without a load.

(5)

Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

(6)

Buck VIN ≥ VOUT + 1 V.

(7)

Limits apply over the entire junction temperature range for operation,

−40°C to +125°C.

7.7

Buck Converters SW1, SW2

Unless otherwise noted, VIN = 3.6 V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2-µH ceramic, and TJ = 25°C.

(1) (2) (3) (4) (5) (6)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VFB

Feedback voltage

–3%(7)

3%(7)

VOUT

Line regulation

2.8 V < VIN < 5.5 V

IOUT = 10 mA

0.089

%/V

Load regulation

100 mA < IOUT < IMAX

0.0013

%/mA

Eff

Efficiency

Load current = 250 mA

96%

ISHDN

Shutdown supply current

EN is de-asserted

0.01

µA

ƒOSC

Internal oscillator frequency

1.7(7)

2.1

MHz

LP3907TL-JSXS/NOPB 数据表(PDF) 8 Page - Texas Instruments

LP3907TL-JSXS/NOPB 数据表(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载