LP3907TL-JSXSSLASHNOPB datasheet(20/58 Pages) TI1

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High PFM Threshold

~1.016 * Vout

Low1 PFM Threshold

~1.008 * Vout

PFM Mode at Light Load

PWM Mode at

Moderate to Heavy

Loads

Pfet on

until

Ipfm limit

reached

Nfet on

drains

inductor

current

until

I inductor = 0

High PFM

Voltage

Threshold

reached,

go into

sleep mode

Low PFM

Threshold,

turn on

PFET

Current load

increases,

draws Vout

towards

Low2 PFM

Threshold

Low2 PFM Threshold,

switch back to PWMmode

Load current

increases

Low2 PFM Threshold

Vout

VIN

80:

IPFM = 66 mA +

LP3907

SNVS511S – JUNE 2007 – REVISED APRIL 2016

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Feature Description (continued)

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage

during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy

load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output

FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output

voltage. If the output voltage is below the low PFM comparator threshold, the PMOS power switch is turned on. It

remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level

set for PFM mode. The typical peak current in PFM mode is:

(4)

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps

to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output

voltage is below the high PFM comparator threshold (see Figure 31), the PMOS switch is again turned on and

the cycle is repeated until the output reaches the desired level. Once the output reaches the high PFM threshold,

the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are

turned off and the part enters an extremely low power mode. Quiescent supply current during this sleep mode is

less than 30 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When

the output drops below the low PFM threshold, the cycle repeats to restore the output voltage to approximately

1.6% above the nominal PWM output voltage.

If the load current increases during PFM mode (see Figure 31) causing the output voltage to fall below the ‘low2’

PFM threshold, the part automatically transitions into fixed-frequency PWM mode.

8.3.2.7 SW1, SW2 Operation

SW1 and SW2 have selectable output voltages ranging from 0.8 V to 3.5 V (typical). Both SW1 and SW2 in the

LP3907 are I2C register controlled and are enabled by default through the internal state machine of the device

following a power-on event that moves the operating mode to the Active state. (See Flexible Power Sequencing

of Multiple Power Supplies.) The SW1 and SW2 output voltages revert to default values when the power-on

sequence has been completed. The default output voltage for each buck converter is factory programmable.

(See Application and Implementation.)

8.3.2.8 SW1, SW2 Control Registers

SW1, SW2 can be enabled/disabled through the corresponding control register.

The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the

functional description. The modulation mode can be overridden by setting I2C bit to a logic 1 in the corresponding

buck control register, forcing the buck to operate in PWM mode regardless of the load condition.

Figure 31. Operation in PFM Mode and Transfer to PWM Mode

LP3907TL-JSXS/NOPB 数据表(PDF) 20 Page - Texas Instruments

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