Logic Interface Characteristics

(1.8V

≤ V

DD_IO

≤ V

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LOGIC INPUTS SS, SI, SCK, PWM_LED

V

IL

Input Low Level

0.5

V

V

IH

Input High Level

V

V

I

I

Logic Input Current

−1.0

1.0

µA

f

SCK

Clock Frequency

V

13

MHz

LOGIC INPUT NRST

V

IL

Input Low Level

0.5

V

V

IH

Input High Level

1.5

V

I

I

Logic Input Current

−1.0

1.0

µA

t

NRST

Reset Pulse Width

10

µs

LOGIC OUTPUT SO

V

OL

Output Low Level

I

0.3

0.5

V

V

OH

Output High Level

I

V

V

V

I

L

Output Leakage Current

V

1.0

µA

SPI Interface

LP3933 is compatible with the SPI serial bus specification

and it operates as a slave. The transmission consists of

16-bit Write and Read Cycles. One cycle consists of 7 Ad-

dress bits, 1 Read/Write (R/W) bit and 8 Data bits. R/W bit

high state defines a Write Cycle and low defines a Read

Cycle. SO output is normally in high-impedance state and it

is active only when Data is sent out during a Read Cycle. A

pull-up or pull-down resistor may be needed in SO line, if a

floating logic signal can cause unintended current consump-

tion in the input where SO is connected. The Address and

Data are transmitted MSB first. The Slave Select signal SS

must be low during the Cycle transmission. SS resets the

interface when high and it has to be taken high between

successive Cycles. Data is clocked in on the rising edge of

the SCK clock signal, while data is clocked out on the falling

edge of SCK.

20080512

SPI Write Cycle

20080511

SPI Read Cycle

www.national.com

7