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HV310 数据表(PDF) 4 Page - Supertex, Inc |
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HV310 数据表(HTML) 4 Page - Supertex, Inc |
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4 / 7 page  4 HV310 ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Timing Diagram GND -48V VIN IIN tSTART contact bounce ILIM PWRGD VUVL tRISE tPWRGD VGATE Initialization Limiting Full On VGATE VOUT tLIM tTH VRAMP V RAMP V GATE inactive active V OUT V IN VGS(th) VGS(lim) VEE tPOR Functional Block Diagram LOGIC V INT VDD UV OV VEE SENSE GATE RAMP V REF UVLO and POR Band Gap Reference Internal Supply Regulator V INT 5kΩ V INT - 1.2V Switch V REF 2V REF Transconductor Buffer PWRGD + - 10mA C C C A C Automatic Restart Delay Circuit Breaker 100mV Note: V INT is the internally regulated supply voltage and can range from 9.0 to 11V. V GS(th) is the gate threshold voltage of the external pass transistor and may be obtained from its datasheet. V GS(lim) is the pass transistor gate-source voltage required to obtain the limit curent. It is dependent on the pass transistor’s characteristics and may be obtained from the transfer characteristics curves on the transistor datasheet. g fs is the transconductance of the pass transistor and may be obtained from its datasheet. R FB is the internal feedback resistor and is 5.0kΩ nominal. 1. 2. 3. 4. 5. I LIM = V SENSE R SENSE t START = 12V C RAMP I RAMP t TH = VGS(th) C RAMP I RAMP t POR = tSTART + tTH t RISE ≈ C RAMP g fs I RAMP - R SENSE 0.9I LIM R FB t LIM ≈ VIN C LOAD - 1 t RISE I LIM 2 t PWRGD = (VINT - VGS(LIM) - 1.2V) C RAMP I RAMP |
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