5

HV310

Functional Description

Insertion Into Hot Backplanes

Telecom, Data Network and some computer applications

require the ability to insert and remove circuit cards from

systems without powering down the entire system. All cir-

cuit cards have some filter capacitance on the power rails,

which is especially true in circuit cards or network terminal

equipment utilizing distributed power systems. The insertion

can result in high inrush currents that can cause damage to

connector and circuit cards and may result in unacceptable

disturbances on the system backplane power rails.

The HV310 was designed to allow the insertion of these cir-

cuit cards or connection of terminal equipment by eliminat-

ing these inrush currents and powering up these circuits in

a controlled manner after full connector insertion has been

achieved. The HV310 is intended to provide this function on

a negative supply rail in the range of -10 to -90V.

Operation

On initial power application an internal regulator seeks to pro-

vide 10V for the internal IC circuitry. Until the proper internal

voltage is achieved all circuits are held reset, the open drain

PWRGD signal is Hi-Z to inhibit the start of any load circuitry

and the gate to source voltage of the external N-channel

MOSFET is held low. Once the internal under voltage lock

out (UVLO) has been satisfied, the circuit checks the input

supply voltage under voltage (UV) and over voltage (OV)

sense circuits to ensure that the input voltage is within ac-

ceptable programmed limits. These limits are determined by

the selected values of resistors R1, R2 and R3, which form

a voltage divider.

Assuming the above conditions are satisfied and while con-

tinuing to hold the PWRGD output inactive and the external

MOSFET GATE voltage low, the current source feeding the

RAMP pin is turned on. The external capacitor connected to

it begins to charge, thus starting an initial time delay deter-

mined by the value of the capacitor. If an interruption of the

input power occurs during this time (i.e. caused by contact

bounce) or the OV or UV limits are exceeded, an immedi-

ate reset occurs and the external capacitor connected to the

RAMP pin is discharged.

When the voltage on the RAMP pin reaches an internally

set voltage limit, the gate drive circuitry begins to turn on the

external MOSFET; allowing the current to softly rise over a

period of a few hundred micro-seconds to the current limit

set point. While the circuit is limiting current, the voltage on

the RAMP pin will be fixed.

Depending on the value of the load capacitance and the

programmed current limit, charging may continue for some

time. The magnitude of the current limit is programmed by

comparing a voltage developed by a sense resistor connect-

ed between the VEE and SENSE pins to 50mV (Typical).

Once the load capacitor has been charged, the current will

drop which will cause the ramp voltage to continue rising;

providing yet another programmed delay.

When the ramp voltage is within 1.2V of the internally regu-

lated voltage, the controller will force the GATE full on and

will pull the PWRGD pin low and the circuit will transition to a

low power standby mode. The PWRGD pin is often used as

an enable for downstream DC/DC converter loads.

At any time during the start up cycle or thereafter, crossing

the UV and OV limits (including hysteresis) will cause an im-

mediate reset of all internal circuitry. Thereafter the start up

process will begin again.

Application Information

Under Voltage and Over Voltage Detection

The UV and OV pins are connected to comparators with

nominal 1.21V thresholds and 100mV of hysteresis (1.21V

± 50mV). They are used to detect under voltage and over

voltage conditions at the input to the circuit. Whenever the

OV pin rises above its threshold or the UV pin falls below its

threshold the GATE voltage is immediately pulled low, the

PWRGD signal is deactivated and the external capacitor

connected to the RAMP pin is discharged.

The under voltage and over voltage trip points can be pro-

grammed by means of the three resistor divider formed by

R1, R2 and R3. Since the input currents on the UV and OV

pins are negligible the resistor values may be calculated as

follows:

UV

OV

Where |V

points.

If we select a divider current of 100µA at a nominal operating

input voltage of 50V then:

(R1+R2+R3) = 50V / 100µA = 500kΩ