CY7C68310
Document 38-08030 Rev. *H
Page 16 of 34
Reserved
Bits (6:1) – must be set to ‘0’.
SRST Enable
Bit (0)
Soft-reset during drive initialization.
‘0’ = Disable soft-reset functionality
‘1’ = Enable soft-reset during drive initialization
0x0A
ATA Data Assert
Bits (7:4)
0x20
ATA cycle times are calculated using Data Assert and Data
Recover values.
Standard values for ATA-compliant devices and a 30.0-MHz
system clock (in binary):
mode 0
0101
(5+1)*33.33 = 200 ns
mode 1
0011
(3+1)*33.33 = 133 ns
mode 2
0011
(3+1)*33.33 = 133 ns
mode 3
0010
(2+1)*33.33 = 100 ns
mode 4
0010
(2+1)*33.33 = 100 ns
ATA Data Recover
Bits (3:0)
Standard recover values and cycle times for ATA-compliant
devices and a 30.0 MHz system clock (in binary):
mode 0
1100
(4+1)+(12+1)*33.33 = 600 ns
mode 1
0111
(3+1)+(7+1)*33.33 = 400 ns
mode 2
0011
(2+1)+(3+1)*33.33 = 233 ns
mode 3
0010
(2+1)+(2+1)*33.33 = 200 ns
mode 4
0000
(2+1)+(0+1)*33.33 = 133 ns
0x0B
ATA Data Set-up
Bits (7:5)
0x00
Set-up time is only incurred on the first data cycle of a burst.
Standard values for ATA-compliant devices and a 30.0 MHz
system clock are (in binary):
mode 0
010
(2+1)*33.33 = 133 ns
mode 1
001
(1+1)*33.33 = 66 ns
mode 2
001
(1+1)*33.33 = 66 ns
mode 3
001
(1+1)*33.33 = 66 ns
mode 4
000
(0+1)*33.33 = 33 ns
Drive Power Valid Polarity
Bit (4)
Controls the polarity of DRVPWRVLD pin.
‘0’ = Active LOW (“connector ground” indication)
‘1’ = Active HIGH (power indication from device)
Override PIO Timing
Bit (3)
This field is used in conjunction with ATA Data Set-up, ATA
Data Assertion, ATA Data Recover, and PIO Mode Selection
fields.
‘0’ = Use timing information acquired from the Drive
‘1’ = Override device timing information with configuration
values
Drive Power Valid Enable
Bit (2)
Table 6-2. EEPROM Organization (continued)
I2C
Address
Field Name
Field Description
Required
I2C Data
Example
I2C Data
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