CY7C68310
Document 38-08030 Rev. *H
Page 28 of 34
8.1
ATA Interface Termination
Design practices as outlined in the ATA/ATAPI-6 specification
for signal integrity should be followed with systems that utilize
a ribbon cable interconnect between the CY7C68310’s ATA
interface and the attached ATA/ATAPI device, especially if
Ultra DMA Mode is utilized.
8.2
Power Supply Regulation
At no time should the 3.3V power rail drop below the 2.5V rail
for proper device operation. Care should be taken to ensure
that the power rails rise and fall without allowing the 3.3V supply
to drop below the 2.5V supply. The recommended method is
to cascade voltage regulating circuits such that the 2.5V supply
is powered from the 3.3V supply.
8.3
Pull-ups/Pull-downs on High-Z Pins
Certain output pins act as open-drain and remain at a high-Z
state unless asserting a ‘0.’ These pins include SCL, SDA,
LOWPWR, and nPWR500. If their functionality is utilized,
these pins must be tied to pull-up resistors to avoid floating
while in a high-Z state. These pins can be left as no-connects
if the functionality is not utilized.
9.0
Manufacturing Interconnect Test Sup-
port
Manufacturing Test Mode is provided as a means to implement
board- and system-level interconnect tests. During Manufac-
turing Test Mode operation, all outputs not associated directly
with USB operation are controllable. Normal state machine
and register control of output pins are disabled. Two vendor-
specific
USB
requests
(LOAD_MFG_DATA
and
READ_MFG_DATA) are used in Manufacturing Test Mode
operation.
9.1
LOAD_MFG_DATA
This USB request is used to enable and control Manufacturing
Test Mode operation. While in Manufacturing Test Mode,
individual pins may be asserted or deasserted depending
upon the contents of the data field. The DD and GPIO pins may
also
be
set
to
a
high-Z
state
in
preparation
for
READ_MFG_DATA command operations. Control of the
select CY7C68310 I/O pins and their high-Z controls are
mapped to the USB data packet associated with this request.
Legal values for wValue are as follows:
• 0x0000
Normal operation mode – returns CY7C68310
to normal operation regardless of previous
command data sets (power-on reset default).
• 0x0001
Manufacturing Test Mode – manufacturing test
registers control specific CY7C68310 outputs
cells to enable board level testing in the manufac-
turing environment.
Legal values for wLength are as follows:
• 0x0000
Valid only when wValue = 0x0000; used when
disabling Manufacturing Test Mode of operation
• 0x0007
Valid only when wValue = 0x0001. For proper
Manufacturing Test Mode operation, wLength must equal
0x0007. Any data packet lengths greater than 7 will result
in a STALL condition.
30MHz
9pF
9pF
1.5K
Ω
CY7C68310
DM
RPU
39
Ω
39
Ω
D+
D-
SDA
1.5K
Ω
3.3V
SCL
3.3V
100
Ω
RREF
AVSS
2.4K
Ω
(1%)
RSDM
1.5K
Ω
DP
RSDP
VBUSPWRVLD
VBUS
62K
Ω
0.1
µF
39K
Ω
Figure 8-1. External Circuitry Requirements
Table 9-1. LOAD_MFG_DATA Command Format
Label
bmRequestType
bRequest
wValue
wIndex
wLength
Data
LOAD_MFG_DATA
0x40
0x05
Disable/Enable
Starting Address
Data Length
Mfg. Test Data
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