TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

28

POST OFFICE BOX 655303

timing characteristics

reset and power up

At initial power up, the TNETE2004 performs an internal reset. No external reset circuitry is required. However,

operation of the TNETE2004 is not specified for 50 ms after power up.

During operation, a full reset of the device can be performed by taking RESET low for a duration of not less than

50

ms. Operation of the device is not ensured for a duration of 5 ms after reset.

receive-data timing

The TNETE2004 buffers have received data in an elastic first-in, first-out (FIFO) buffer so that it can be

synchronous to the TNETE2004 10-MHz clock. At the start of packet reception on the RCVP/RCVN pair, no

more than five bits can be received and not be forwarded to RXD.

The selected compatibility mode (see Table 2) of the PHY affects on which clock edge (rising or falling) the

received data is valid. Figure 18 through Figure 21 show the receive timing for compatibility modes of operation,

and the respective receive-data timing tables show the setup and hold timings. The only differences between

modes are the polarity changes in RXCLK, CRS, and RXD during idle periods.

mode 1 receive-data timing

MIN

TYP

MAX

UNIT

tRDLAT

Receive-data latency

500

ns

tPD

Receive data

40

60

ns

tCRSHO

Time from receiver idle to carrier sense off

200

ns

RCVP/

RCVN

RXCLK

(see Note A)

CRS

tRDLAT

tCRSHO

tPD

RXD

(see Note B)

NOTES: A. RXCLK is continuous.

B. During a collision, the data output on RXD is not valid received data (or looped-back transmit data) since the digital PLL is acquiring

lock to a different source of incoming data.

Figure 18. Mode 1 Receive Timing