TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

38

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels

are compatible with TTL devices.

Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the

level at which the signal no longer is considered high is 2 V. The level at which the signal is considered low is 0.8 V.

For a low-to-high transition, the level at which the signal no longer is considered low is 0.8 V, and the level at which

the signal is considered high is 2 V, as shown in the following diagram.

The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically

1.5 ns.

2 V (high)

0.8 V (low)

test measurement

The test and load circuits shown in Figure 30 represent the programmable load of the tester-pin electronics used

to verify timing parameters of the TNETE2004 output signals.

(c) XMTP AND XMTN TEST LOAD (ac TESTING)

(b) IREF TEST CIRCUIT

(a) TTL OUTPUT TEST LOAD

180

Ω

IREF

CL

IOH

VLOAD

IOL

Test

Point

TTL

Output

Under

Test

Where:

IOH

= Refer to IOH in dc electrical characteristics.

IOL

= Refer to IOL in dc electrical characteristics.

VLOAD = 1.5 V, typical dc-level verification or

0.7 V, typical timing verification

CL

= 22 pF, typical load-circuit capacitance

50

Ω

50

Ω

Test

Point

Test

Point

XMTN

50

Ω

50

Ω

50

Ω

Test

Point

XMTN

XMTP

25

Ω

25

Ω

XMTP

50

Ω

X2

(d) XMTP AND XMTN TEST LOAD (dc TESTING)

X2–Fil–Mag 23Z128 1: 2

Figure 30. Test and Load Circuit