TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

11

POST OFFICE BOX 655303

functional description

The TNETE2004 consists of four PHYs, with each PHY having several logical blocks (see the functional block

diagram and Table 1).

Table 1. Logical Blocks

LOGICAL BLOCKS

FUNCTION

Transmitter function

Accepts data from the data terminal equipment (DTE) and transmits it onto the network

Receiver function

Receives data from the network and sends it to the DTE

Collision/signal-quality error detection

Indicates to the DTE any collision on the network/transmitter with valid link

Jabber detection

Indicates to the DTE if a packet transmission exceeds 20-ms minimum

Auto-negotiation

Negotiate to establish the highest common protocol

Management-data interface

To allow register-based management operations for each PHY module

Link test

A link pulse is sent to indicate a valid connection.

LED status indicator

Indication for link, activity, and collision

Test port

IEEE Std 1149.1 test-access port and boundary-scan testing

Loopback test mode

Loopback capabilities are provided to allow certain tests to be performed to validate operation of

the TNETE2004.

Compatibility modes

Ease connection to third-party MACs

10BASE-T differential line-transmitter function

Each differential line driver of the TNETE2004 drives a balanced, properly terminated twisted-pair transmission

line with a characteristic impedance of 85

Ω to 111 Ω (see Figure 2). In the idle state, the driver maintains a

minimum differential output voltage, while staying within the required common-mode voltage range.

The driver incorporates an on-chip wave-shaping stage and a high-frequency filtering stage to allow the outputs

to be connected directly to isolation transformers through serial termination resistors. No external filters are

required.

Serial data for transmission by a PHY is presented to the appropriate transmit data (TXD) input of the

TNETE2004. To be valid, data must be synchronized on the appropriate edges of the transmit clock (TXCLK)

signal, which depends on the compatibility-mode setting.

Once the transmit-enable (TXEN) pin is deasserted for a PHY, the driver maintains full differential outputs for

a minimum of 250 ns, which then begins to decay to minimum differential levels.

The PHY also transmits regular link pulses in compliance with IEEE Std 802.3.

10BASE-T differential line-receiver function

The line-receiver pins of each PHY must be connected to a properly terminated transmission line by an external

isolation transformer. The receiver establishes its own common-mode input-bias voltage. Data received from

the network is output on RXD of the appropriate PHY and synchronized by the appropriate edges of the

corresponding RXCLK signal, which depends on the compatibility-mode setting.

The receiver incorporates a squelch function to pass incoming data. This smart squelch function passes data

only if the input amplitude is greater than a minimum signal threshold and if a specific pulse sequence is

received. This protects input data from impulse line noise being mistaken for signal or link activity. The squelch

circuits quickly deactivate if received pulses exceed the specifications; thus, overly long pulses are not mistaken

as link pulses.

Carrier sense (CRS) is driven high while the squelch function is active to indicate that the circuit is allowing data

to pass from the twisted pair. CRS is driven low when the squelch circuit is disabling data low.