PC87365 datasheet(39/215 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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transmission of the new value of PIRQ3 during slot 3 of the SERIRQ bus. No polarity adjustment occurs during this transla-

tion process. Therefore, when the level of a PIRQn pin goes high or low, the result is transmitted with no polarity adjustment

during slot “n” of the SERIRQ bus.

The Interrupt Serializer is controlled by bit 6, Pins 117-127 Select PIRQ, of SuperI/O Configuration 1 register. When this bit

is set to 0 (default), the Interrupt Serializer is disabled. When it is set to 1, the Interrupt Serializer is enabled and each PIRQn

input function is selected on its associated pin. The PIRQn input value is then routed to the Interrupt Serializer as the IRQ

value to be driven onto IRQ slot “n” when at least one of the following conditions is true:

Slot “n” is not selected by any internal IRQ source.

Slot “n” is selected by an internal IRQ source which is set for sharing (low polarity).

Otherwise, the IRQ value driven onto IRQ slot “n” is the value of any internal IRQ that is selected.

2.4

PROTECTION

The PC87365 provides features to protect the PC at mechanical and software levels.

At the mechanical level, the device can detect intrusion to the chassis of the PC. It can also control the solenoids that lock

and unlock the chassis.

At the hardware level, the device can disable I/O port access. This protects system integrity by enabling the primary oper-

ating software to prevent other unwanted I/O operations by other software.

At the software level, the device can be locked to protect configuration bits or alteration of the hardware configuration of the

device, as well as internal GPIO settings and several types of configuration settings.

All protection mechanisms can optionally be used.

2.4.1

Chassis Intrusion Detection

The Chassis Intrusion Detection mechanism is based on the state of pin 29, CHASI. This pin reflects the status of an external

switch that indicates the PC chassis state.

Bits 4,5 of the SIOCFB register monitor this pin and provide two types of information. Bit 4 reports a previously detected

chassis intrusion, defined as any kind of transition on the CHASI pin. Bit 5 reflects the momentary value of the CHASI pin.

For further details on the SIOCFB register, see Section 2.9.11.

To prevent the CHASI pin from detecting a false chassis intrusion, it is implemented with an internal noise filter.

A chassis intrusion event can be reported to the host system by either software or hardware. When using software, the sys-

tem must read the SIOCFB register to check if an intrusion event has occurred. When using hardware, the device provides

the following means for indicating chassis intrusion:

Dedicated output (CHASO).

SMI assertion.

To use the CHASO function, it must first be selected by setting bit 6 of the SIOCFA register to 1. Thereafter, whenever a

chassis intrusion is detected, the CHASO pin reflects the value of bit 4 of the SIOCFB register. When bit 4 of this register is

set to 1, the CHASO pin is asserted (driven low). It is de-asserted when this bit is cleared.

To use the SMI assertion, it must either be selected on its pin or routed to interrupt request channel 2. To select SMI on its

pin, set bit 2 of the SIOCF3 register to 1 (for further details, see Section 2.9.4). To route the SMI signal to interrupt request

channel 2, set bit 4 of the SIOCF5 register to 1 (for further details, see Section 2.9.6). In addition, the chassis intrusion event

must be routed to the SMI signal by setting bit 5 of the SIOCF8 register to 1 (for further details, see Section 2.9.9). Thereafter,

whenever a chassis intrusion is detected, the SMI signal reflects bit 4 of the SIOCFB register. When bit 4 of this register is

set to 1, the SMI signal and the selected target indication are asserted (driven low). The SMI signal is de-asserted when this

bit 4 is cleared.

2.4.2

Chassis Lock and Unlock

The Chassis Lock and Unlock mechanism is based on the output functions of pin 1, CHLOCK and pin 128, CHUNLOCK, as

well as the values of bits 2, 3 of the SIOCF5 register. A lock operation is defined as the assertion of CHLOCK for approxi-

mately the next 0.75 seconds and an unlock operation as the assertion of CHUNLOCK for the same duration of time.

To use this mechanism, CHLOCK and CHUNLOCK must first be selected on their respective pins. To select CHLOCK, write

10 to bits 1-0 of the SIOCF2 register. To select CHUNLOCK, write 10 to bits 1-0 of the SIOCF5 register. The CHLOCK and

CHUNLOCK functions can then be operated using bits 2 and 3 of the SIOCF5 register.

Bit 3 of the SIOCF5 register determines if the operation to be performed will be lock or unlock. When set to 0, unlock is se-

lected; when set to 1, lock is selected.

Writing to bit 2 of the SIOCF5 register initiates the operation set by bit 3 and reflects the status of the lock/unlock mechanism.

Before initiating any lock/unlock operation, bit 2 must be verified to be 0. This indicates that the lock/unlock mechanism is

idle and can be used to perform a new operation. When bit 3 is set to the desired value and bit 2 is verified to be 0, bit 2 can

be set to 1 to initiate the operation determined by bit 3.

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