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2.0 Device Architecture and Configuration (Continued)

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2.9

SUPERI/O CONFIGURATION REGISTERS

This section describes the SuperI/O configuration and ID registers (those registers with first level indexes in the range of 20h

- 2Eh). See Table 16 for a summary and directory of these registers.

Table 16. SuperI/O Conﬁguration Registers

Index Mnemonic

Power Well

Type

Section

20h

SID

SuperI/O ID

VDD

2.9.1

21h

SIOCF1

SuperI/O Conﬁguration 1

VDD

R/W

2.9.2

22h

SIOCF2

SuperI/O Conﬁguration 2

VDD

R/W

2.9.3

23h

SIOCF3

SuperI/O Conﬁguration 3

VDD

R/W

2.9.4

24h

SIOCF4

SuperI/O Conﬁguration 4

VDD

R/W

2.9.5

25h

SIOCF5

SuperI/O Conﬁguration 5

VDD

R/W

2.9.6

27h

SRID

SuperI/O Revision ID

VDD

2.9.8

28h

SIOCF8

SuperI/O Conﬁguration 8

VDD

R/W

2.9.9

2Ah

SIOCFA

SuperI/O Conﬁguration A

VPP

R/W

2.9.10

2Bh

SIOCFB

SuperI/O Conﬁguration B

VPP

R/W

2.9.11

2Ch

SIOCFC

SuperI/O Conﬁguration C

VPP

R/W

2.9.12

2Dh

SIOCFD

SuperI/O Conﬁguration D

VPP

R/W

2.9.13

2Eh

Reserved exclusively for National use

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