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PC87365 数据表(PDF) 113 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 PC87365
功能描述  128-Pin LPC SuperI/O with System Hardware Monitoring
PDF  215 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

PC87365 数据表(HTML) 113 Page - National Semiconductor (TI)

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3.0 System Wake-Up Control (SWC) (Continued)
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Event Configuration
Each pin in the SBGPIO port is a potential input event source. The event detection can trigger a system notification upon predeter-
mined behavior of the source pin. The SBGPIO Pin Configuration register determines the event detection trigger type for the system
notification.
Event Type and Polarity - One trigger type of event detection is supported: edge (Event Type, bit 4 = 0). An edge event
may be detected upon a source pin transition either from high to low or low to high. The direction of the transition (i.e.,
edge) is determined by Event Polarity (bit 5).
Event Debounce Enable - The input signal can be debounced for about 15 msec before entering the detector. The signal
state is transferred to the detector only after a debouncing period during which the signal has no transitions, to ensure
that the signal is stable. The debouncer adds 15 msec delay to both assertion and de-assertion of the event pending
indicator. Therefore, when working with a level event and system notification by either SMI or IRQ, it is recommended
to disable the debounce if the delay in the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event
Debounce Enable (bit 6 of the SBGPIO Pin Configuration register).
3.4.31
Standby GPIO Pin Select Register (SBGPSEL)
This register selects the GPIOE/GPIE pin (port number and pin number) to be configured (the register accessed by the
Standby GPIO Pin Configuration register). This register is reset to 00h on VPP power-up or software reset.
When port 0 is selected, bits 2-0 select between pins GPIE7,6 and GPIOE5-0. When port 1 is selected, bits 2-0 select be-
tween pins GPOS0 and GPOS1. Pins GPIS2 and GPIS3 are input only and require no configuration.
Location:
Bank 3, Offset 13h
Type:
R/W
Bit
76543210
Name
Reserved
Port Select
Reserved
Pin Select
Reset
00000000
Bit
Description
7-5
Reserved.
4
Port Select. This bit selects the GPIO port to be configured.
0: Port 0 (default)
1: Port 1
3
Reserved.
2-0
Pin Select. These bits select the GPIO pin to be configured in the selected port.
000, 001, ... 111:The binary value of the pin number, 0, 1, ... 7 respectively (default=0)



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