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PC87365 数据表(PDF) 121 Page - National Semiconductor (TI) |
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PC87365 数据表(HTML) 121 Page - National Semiconductor (TI) |
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121 / 215 page  121 www.national.com 4.0 Fan Speed Control 4.1 OVERVIEW This chapter describes a generic Fan Speed Control module. For the implementation used in this device, see the Device Architecture and Configuration chapter. The Fan Speed Control is a programmable Pulse Width Modulation (PWM) generator. The PWM generator output is used to control the fan’s power voltage, which is correlated to the fan’s speed. Convertinga0to 100% duty cycle PWM signal to an analog voltage range is achieved by an external circuit, as shown in Figure 14. Some newer fans accept direct PWM input without any external circuitry. When an overtemperature condition is detected, the Fan speed Control forces the fan to turn on at 100% duty cycle. Figure 14. Fan Speed Control - System Configuration 4.2 FUNCTIONAL DESCRIPTION The PWM generator operation is based on a PWM counter and two registers: the Fan Speed Control Pre-Scale register (FCPSR), used to determine the overall cycle time (or the frequency) of the FANOUT output, and the Fan Speed Control Duty Cycle register (FCDCR), used to determine the duty cycle of the FANOUT between 0 to 100%. The PWM counter is an 8-bit, free-running counter that runs continuously in a cyclic manner, i.e., its cycle equals 256 clock periods. The PWM output is high, as long as the count is lower than the FCDCR value and it flips to low as the counter ex- ceeds that value. The duty cycle (expressed as a percentage) is therefore (FCDCR/256)*100. In particular, the PWM output is continuously low when FCDCR=0 and continuously high when FCDCR=FFh. The FANOUT output may be inverted by an external configuration bit, in which case the FANOUT duty cycle is ([256-FCDCR]/256)*100. The PWM counter clock is generated by dividing the input clock (either 24 MHz or 200 KHz), using a clock divider. The di- vision factor, which must be between 1 and 124, is defined as Pre-Scale Value+1, where Pre-Scale is the binary value stored in bits 6 to 0 of the FCPSR register. The resulting PWM output frequency is therefore: (24 MHz or 200 kHz/([Pre-Scale Value+1] *256). The default selection of 24 MHz input clock allows a programmable FANOUT frequency in the range of 756 Hz to 93.75 KHz. For lower frequencies, selecting the 200 KHz input clock allows a frequency range of 6 Hz to 781 Hz (see Figure 15). The FANOUT frequency must be pre-selected according to the fan type’s specific requirements prior to enabling the Fan Speed Control. The only run-time change that is required to dynamically control the fan speed is the value of the FCDCR register. Warning! The contents of the FCPSR register must not be changed when the Fan Speed Control is enabled. Enable Fans on OTS Detection When the respective Fan i Enable on OTS (bits 2-0) of the Fan Speed Control OTS Con- figuration register is set (see Section 2.18.5 on page 77), the fan is forced to 100% duty cycle when any of the temperature measurement channels flags an overtemperature condition. This occurs regardless of the setting of the FCDCR register in order to help protect the system from overheating. Fan Speed Control Fan FANOUT Control External Circuitry External Circuitry 24 MHz (1-124) PWM FCDCR Register FCDCR > Counter FANOUT FCPSR Register Figure 15. PWM Generator (FANOUT) O Invert 0 1 200 KHz Bit 7 Bits 6-0 PWM Output - Counter Comparator 0 1 FANOUT Clock Divider |
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