ASX340CS datasheet(57/74 Pages) ONSEMI

57 / 74 page

ASX340CS_DS Rev. F Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Modes and Timing

Figure 39:

Power Up Sequence

Notes:

1. RESET_BAR may not exceed VDD_IO + 0.3V.

2. The 2.8V plane (VAA, VAA_PIX, VDD_PLL, VDD_DAC, VDD_IO) must remain at a higher voltage than

the 1.8V core voltage at all times.

Notes:

1. Xtal settling time is component-dependent (Xtal, Oscillator, and so on) and usually takes about

10ms ~100ms.

2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are

required for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is

performed by the RC circuit, then the RC time must include the all power rail settle time and Xtal.

Table 29:

Power Up Sequence

Definition

Symbol

Minimum

Typical

Maximum

Unit

VDD_PLL to VAA/VAA_PIX

–

s

VAA/VAA_PIX to VDD_IO

–

s

VDD_IO to VDD

–

s

Xtal settle time

–

301

–ms

Hard Reset

102

––

Clock cycle

Internal Initialization

–

VDD (1.8)

VAA_PIX

VAA (2.8)

VDD_PLL

VDD_DAC (2.8)

EXTCLK

RESET_BAR

VDD_IO (2.8)

Hard Reset

Internal

(NTSC/PAL)

Initialization

Patch Config

SPI or Host

Streaming

ASX340CS 数据表(PDF) 57 Page - ON Semiconductor

ASX340CS 数据表(HTML) 57 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

数据表下载