ASX340CS datasheet(58/74 Pages) ONSEMI

58 / 74 page

ASX340CS_DS Rev. F Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Modes and Timing

Figure 40:

Power Down Sequence

(1) t3 is required between power down and next power up time, all decoupling caps from

regulators must completely discharged before next power up.

Figure 41:

FRAME_SYNC to FRAME_VALID/LINE_VALID

Table 30:

Power Down Sequence

Definition

Symbol

Minimum

Typical

Maximum

Unit

VDD to VDD_IO

0––

s

VDD_IO to VAA/VAA_PIX

0––

s

VAA/VAA_PIX to VDD_PLL/DAC

0––

s

Power Down until Next Power Up Time

1001

––

Table 31:

FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters

Parameter

Name

Conditions

Min

Typ

Max

Unit

FRAME_SYNC to FV/LV

tFRMSYNC_FVH

Auto Config mode

1.21

–

tFRAME_SYNC

tFRAMESYNC

VDD (1.8)

VAA_PIX

VAA (2.8)

VDD_PLL

VDD_DAC (2.8)

EXTCLK

VDD_IO (2.8)

Power Down until next Power Up Cycle

FRAME_SYNC

FRAME_VALID

LINE_VALID

tFRAME_SYNC

tFRMSYNH_FVH

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